A novel low power time-mode comparator for successive approximation register ADC. - Sekedi B. Kobenge; Huazhong Yang (IEICE Electron. Express, 2009)

A 250KS/s, 0.8V ultra low power successive approximation register ADC using a Dynamic rail-to-rail comparator. - Sekedi B. Kobenge; Huazhong Yang (IEICE Electron. Express, 2010)

Design considerations for low power time-mode SAR ADC. - Hua Fan 001; Xue Han; Sekedi B. Kobenge; Qi Wei 001; Huazhong Yang (Int. J. Circuit Theory Appl., 2014)