Effects of Voltage and Temperature Variations on the Electrical Masking Capability of Sub-65 nm Combinational Logic Circuits. - Semiu A. Olowogemo; William H. Robinson; Daniel B. Limbrick (DFT, 2018)

Pulse Broadening in Combinational Circuits with Standard Logic Cell Synthesis. - Semiu A. Olowogemo; William H. Robinson; Ahmed Yiwere; Ebenezer Tachie-Menson; Daniel B. Limbrick; Bor-Tyng Lin (MWSCAS, 2019)

Electrical Masking Improvement with Standard Logic Cell Synthesis Using 45 nm Technology Node. - Semiu A. Olowogemo; Ahmed Yiwere; Bor-Tyng Lin; Hao Qiu; William H. Robinson; Daniel B. Limbrick (MWSCAS, 2020)

Gem5Panalyzer: A Light-weight tool for Early-stage Architectural Reliability Evaluation & Prediction. - Hao Qiu; Xiaoxing Qiu; Semiu A. Olowogemo; Bor-Tyng Lin; William H. Robinson; Daniel B. Limbrick (MWSCAS, 2020)

Evaluating Soft Error Mitigation Trade-offs During Early Design Stages. - Hao Qiu; Bor-Tyng Lin; Semiu A. Olowogemo; William H. Robinson; Daniel B. Limbrick (ARCS, 2021)

Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies. - Semiu A. Olowogemo; Hao Qiu; Bor-Tyng Lin; William H. Robinson; Daniel B. Limbrick (DFT, 2022)

Understanding time-varying vulnerability accross GPU Program Lifetime. - Hao Qiu; Semiu A. Olowogemo; Bor-Tyng Lin; William H. Robinson; Daniel B. Limbrick (DFT, 2022)