A 0.6-1.8 V/0.4-1.6 V Input/Output LDO with High PSRR over 50 dB/30 dB in Dual-Modes. - Siwan Dong; Sen Bu; Xingyuan Tong (Circuits Syst. Signal Process., 2023)

A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCs. - Siwan Dong; Changxiang Liu; Sen Bu; Jiaqi Li (Circuits Syst. Signal Process., 2023)