New impulse sampled IIR switched-capacitor interpolators. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ICECS, 1996)

A novel half-band SC architecture for efficient analog impulse sampled interpolation. - Seng-Pan U; Rui Paulo Martins; José E. Franca (ICECS, 1998)

Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (2), 1999)

High performance multirate SC circuits with predictive correlated double sampling technique. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (2), 1999)

A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction. - Seng-Pan U; Rui Paulo Martins; José E. Franca (ISCAS, 2000)

High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (1), 2001)

A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (1), 2001)

N-path multirate sigma-delta modulator for high-frequency applications. - Fan Lou; Seng-Pan U; Rui Paulo Martins (ICECS, 2002)

Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. - Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (4), 2002)

A very area/power efficient mixed signal circuit for voice signal processing in 0.18 digital technology. - João Risques; Jorge Duarte; Vasco Amaro; Seng-Pan U; Kuok Vai Chiang; Ka Fai Chang; Keng Chong Lai (ESSCIRC, 2003)

Quantitative noise analysis of jitter-induced nonuniformly sampled-and-held signals. - Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ICASSP (6), 2003)

Frequency-downconversion and IF channel selection A-DQS sample-and-hold pair for two-step-channel-select low-IF receiver. - Pui-In Mak; Chi-sam Sou; Seng-Pan U; Rui Paulo Martins (ICECS, 2003)

A front-to-back-end modeling of I/Q mismatch effects in a complex-IF receiver for image-rejection enhancement. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (ICECS, 2003)

A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. - Chon-In Lao; Ho-leng Leong; Kuoi-Fok Au; Kuok-Hang Mok; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2003)

Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; José E. Franca (ISCAS (1), 2003)

An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. - Pui-In Mak; Kin-Kwan Ma; Weng-leng Mok; Chi-sam Sou; Kit-man Ho; Cheng-Man Ng; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2004)

A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS (4), 2004)

A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems. - Pui-In Mak; Man-Chung Wong; Seng-Pan U. (ISCAS (5), 2004)

A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2004)

A 2.5-V 57-MHz 15-tap SC bandpass interpolating filter with 320-MS/s output for DDFS system in 0.35-μ hboxm CMOS. - Seng-Pan U; Rui Paulo Martins; José E. Franca (IEEE J. Solid State Circuits, 2004)

Exact spectra analysis of sampled signals with jitter-induced nonuniformly holding effects. - Seng-Pan U.; Sai-Weng Sin; Rui Paulo Martins (IEEE Trans. Instrum. Meas., 2004)

A 1-V transient-free and DC-offset-canceled PGA with a 17.1-MHz constant bandwidth over 52-dB control range in 0.35-μm CMOS. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (CICC, 2005)

A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. - Kin-Sang Chio; Seng-Pan U.; Rui Paulo Martins (ISCAS (4), 2005)

A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. - Ka-Hou Ao Ieong; Chong-Yin Fok; Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS (1), 2005)

A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. - Chon-In Lao; Seng-Pan U.; Rui Paulo Martins (ISCAS (4), 2005)

A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (2), 2005)

A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS (2), 2005)

Two-step channel selection-a novel technique for reconfigurable multistandard transceiver front-ends. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. - Ka-Hou Ao Ieong; Seng-Pan U.; Rui Paulo Martins (APCCAS, 2006)

A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy. - Kin-Sang Chio; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator. - Chon-In Lao; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. - Jun-Xia Ma; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2006)

A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. - Weng-leng Mok; Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2007)

Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers. - Pui-In Mak; Seng-Pan U; Rui Paulo Martins (IET Circuits Devices Syst., 2007)

A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs. - U. Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique. - Li Ding; Sio Chan; Kim-Fai Wong; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller. - Ngai Kong; Seng-Pan U; Rui Paulo Martins (APCCAS, 2008)

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems. - He Gong Wei; U. Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A 1-V 90dB DR audio stereo DAC with embedding headphone driver. - Kim-Fai Wong; Ka-Ian Lei; Seng-Pan U; Rui Paulo da Silva Martins (APCCAS, 2008)

A power-efficient capacitor structure for high-speed charge recycling SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ICECS, 2008)

A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. - He Gong Wei; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2008)

On the Design of a Programmable-Gain Amplifier With Built-In Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems. - Pui-In Mak; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch. - Sai-Weng Sin; U-Fat Chio; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps. - Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

An efficient DAC and interstage gain error calibration technique for multi-bit pipelined ADCs. - Li Ding; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (APCCAS, 2010)

A reduced jitter-sensitivity clock generation technique for continuous-time ΣΔ modulators. - Yang Jiang 002; Kim-Fai Wong; Chen-Yan Cai; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2010)

An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H. - Sai-Weng Sin; Li Ding; Yan Zhu 001; He Gong Wei; Chi-Hang Chan; U. Fat Chio; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (ESSCIRC, 2010)

A Fixed-Pulse Shape Feedback Technique with reduced clock-jitter sensitivity in Continuous-Time sigma-delta modulators. - Yang Jiang 002; Kim-Fai Wong; Chen-Yan Cai; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ICECS, 2010)

An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications. - Guohe Yin; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Zhihua Wang 001 (ICECS, 2010)

A voltage feedback charge compensation technique for split DAC architecture in SAR ADCs. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2010)

1.2-V, 10-bit, 60-360 MS/s time-interleaved pipelined analog-to-digital converter in 0.18 μm CMOS with minimised supply headroom. - Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IET Circuits Devices Syst., 2010)

A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2010)

Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC. - U-Fat Chio; He Gong Wei; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Rapid Power-Switchable Track-and-Hold Amplifier in 90-nm CMOS. - He Gong Wei; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs. - Yan Zhu 001; U. Fat Chio; He Gong Wei; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (VLSI Design, 2010)

A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (A-SSCC, 2011)

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS. - Chi-Hang Chan; Yan Zhu 001; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators. - Si-Seng Wong; U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2011)

A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration. - U. Fat Chio; Chi-Hang Chan; Hou-Lon Choi; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ESSCIRC, 2011)

Hybrid loopfilter sigma-delta modulator with NTF zero compensation. - Arshad Hussain; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISOCC, 2011)

A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS. - He Gong Wei; Chi-Hang Chan; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (ISSCC, 2011)

A robust NTF zero optimization technique for both low and high OSRs sigma-delta modulators. - Yun Du; Tao He; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A DT 0-2 MASH ΣΔ modulator with VCO-based quantizer for enhanced linearity. - Tao He; Yun Du; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A 10-bit SAR ADC with two redundant decisions and splitted-MSB-cap DAC array. - Wen-Lan Wu; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (APCCAS, 2012)

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC. - Si-Seng Wong; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (CICC, 2012)

A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique. - Rui Wang; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Zhihua Wang 001; Rui Paulo Martins (ESSCIRC, 2012)

A 0.024 mm2 4.9 fJ 10-bit 2 MS/s SAR ADC in 65 nm CMOS. - Guohe Yin; He Gong Wei; U-Fat Chio; Sai-Weng Sin; Seng-Pan U.; Zhihua Wang 001; Rui Paulo Martins (ESSCIRC, 2012)

A 10MHz BW 78dB DR CT ΣΔ modulator with novel switched high linearity VCO-based quantizer. - Tao He; Yang Jiang 002; Yun Du; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2012)

An ELD tracking compensation technique for active-RC CT ΣΔ modulators. - Chen-Yan Cai; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (MWSCAS, 2012)

A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

A 3.8mW 8b 1GS/s 2b/cycle interleaving SAR ADC with compact DAC structure. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (VLSIC, 2012)

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC. - He Gong Wei; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A 50-fJ 10-b 160-MS/s Pipelined-SAR ADC Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation. - Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2012)

A continuous-time VCO-assisted VCO-based ΣΔ modulator with 76.6dB SNDR and 10MHz BW. - Yun Du; Tao He; Yang Jiang 002; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2013)

A 0.6V 8b 100MS/s SAR ADC with minimized DAC capacitance and switching energy in 65nm CMOS. - Wen-Lan Wu; Yan Zhu 001; Li Ding; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U.; Rui Paulo Martins (ISCAS, 2013)

A background gain- calibration technique for low voltage pipelined ADCs based on nonlinear interpolation. - Li Ding; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (MWSCAS, 2013)

A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE J. Solid State Circuits, 2013)

A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC. - Si-Seng Wong; U-Fat Chio; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2013)

An 11b 900 MS/s time-interleaved sub-ranging pipelined-SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2014)

Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators. - Da Feng; Franco Maloberti; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISCAS, 2014)

Split-SAR ADCs: Improved Linearity With Power and Speed Optimization. - Yan Zhu 001; Chi-Hang Chan; U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2015)

26.5 A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISSCC, 2015)

20.4 A 123-phase DC-DC converter-ring with fast-DVS for microprocessors. - Yan Lu 002; Junmin Jiang; Wing-Hung Ki; C. Patrick Yue; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISSCC, 2015)

Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs. - Jianyu Zhong; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A digital LDO with transient enhancement and limit cycle oscillation reduction. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (APCCAS, 2016)

A 0.011mm2 60dB SNDR 100MS/s reference error calibrated SAR ADC with 3pF decoupling capacitance for reference voltages. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Chon-Lam Lio; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2016)

A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration. - Lei Qiu 002; Kai Tang 002; Yan Zhu 001; Liter Siek; Yuanjin Zheng; Seng-Pan U (A-SSCC, 2016)

A high DR multi-channel stage-shared hybrid front-end for integrated power electronics controller. - Yuan Ren; Sai-Weng Sin; Chi-Seng Lam; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2016)

A 12b 180MS/s 0.068mm2 pipelined-SAR ADC with merged-residue DAC for noise reduction. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2016)

A 94-dB DR, 105-Hz bandwidth interface circuit for inertial navigation applications. - Wei Li; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (ISIC, 2016)

A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

An 11b 450 MS/s Three-Way Time-Interleaved Subranging Pipelined-SAR ADC in 65 nm CMOS. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2016)

A Fully Integrated Digital LDO With Coarse-Fine-Tuning and Burst-Mode Operation. - Mo Huang; Yan Lu 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators. - Mo Huang; Yan Lu 002; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Wing-Hung Ki (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC. - Yan Zhu 001; Chi-Hang Chan; Si-Seng Wong; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC. - Jianwei Liu 005; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo da Silva Martins (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 5-bit 2 GS/s binary-search ADC with charge-steering comparators. - U. Fat Chio; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (A-SSCC, 2017)

A 5.35 mW 10 MHz bandwidth CT third-order ΔΣ modulator with single Opamp achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS. - Wei Wang 177; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2017)

A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC. - Guan-Cheng Wang 002; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (ESSCIRC, 2017)

CCM operation analysis and parameters design of Negative Output Elementary Luo Converter for ripple suppression. - Chi-Wa U; Chi-Seng Lam; Man-Kay Law; Sai-Weng Sin; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (IECON, 2017)

A digital PWM controlled KY step-up converter based on frequency domain ΣΔ ADC. - Xia Du; Chi-Seng Lam; Sai-Weng Sin; Man-Kay Law; Franco Maloberti; Man-Chung Wong; Seng-Pan U; Rui Paulo Martins (ISIE, 2017)

16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibration. - Chi-Hang Chan; Yan Zhu 001; Iok-Meng Ho; Wai-Hong Zhang; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. - Kostas Doris; David Robertson 002; Seung-Tak Ryu; Seng-Pan U (ISSCC, 2017)

20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop control. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiency. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOS. - Junmin Jiang; Yan Lu 002; Wing-Hung Ki; Seng-Pan U; Rui Paulo Martins (ISSCC, 2017)

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration. - Chi-Hang Chan; Yan Zhu 001; Cheng Li 010; Wai-Hong Zhang; Iok-Meng Ho; Lai Wei; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2017)

A sub-1V 78-nA bandgap reference with curvature compensation. - Ziyang Luo; Yan Lu 002; Mo Huang; Junmin Jiang; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (Microelectron. J., 2017)

Metastablility in SAR ADCs. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Boris Murmann; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 7.8-mW 5-b 5-GS/s Dual-Edges-Triggered Time-Based Flash ADC. - Chi-Hang Chan; Yan Zhu 001; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins; Franco Maloberti (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. - Yan Lu 002; Haojuan Dai; Mo Huang; Man-Kay Law; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing. - Liang Qi 002; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 12b 180MS/s 0.068mm2 With Full-Calibration-Integrated Pipelined-SAR ADC. - Jianyu Zhong; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations. - Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications. - Arshad Hussain; Sai-Weng Sin; Chi-Hang Chan; Ben Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial $V_{ mathrm {cm}}$ -Based Switching. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Sai-Weng Sin; Fan Ye 001; Junyan Ren; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A dual-output SC converter with dynamic power allocation for multicore application processors. - Junmin Jiang; Yan Lu 002; Xun Liu; Wing-Hung Ki; Philip K. T. Mok; Seng-Pan U; Rui Paulo Martins (ASP-DAC, 2018)

A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler. - Wenning Jiang; Yan Zhu 001; Chi-Hang Chan; Boris Murmann; Seng-Pan U; Rui Paulo Martins (A-SSCC, 2018)

A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT. - Fangyu Mao; Yan Lu 002; Jie Lin; Chenchang Zhan; Seng-Pan U; Rui Paulo Martins (ISCAS, 2018)

A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency. - Fangyu Mao; Yan Lu 002; Seng-Pan U.; Rui Paulo Martins (ISSCC, 2018)

A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems. - Fangyu Mao; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (VLSI-DAT, 2018)

A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (VLSI Circuits, 2018)

A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration. - Chi-Hang Chan; Yan Zhu 001; Wai-Hong Zhang; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator. - Mo Huang; Yan Lu 002; Seng-Pan U; Rui Paulo Martins (IEEE J. Solid State Circuits, 2018)

Quick and cost-efficient A/D converter static characterization using low-precision testing signal. - Wei Wei Qin; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (Microelectron. J., 2018)

Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology. - Xiaofeng Yang 004; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. - Lei Qiu 002; Kai Tang 002; Yuanjin Zheng; Liter Siek; Yan Zhu 001; Seng-Pan U (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Passive Noise Shaping in SAR ADC With Improved Efficiency. - Yan Song; Chi-Hang Chan; Yan Zhu 001; Li Geng; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area. - Guan-Cheng Wang 002; Yan Zhu 001; Chi-Hang Chan; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A High DR High-Input-Impedance Programmable-Gain ECG Acquisition Interface with Non-inverting Continuous Time Sigma-Delta Modulator. - Junhao Liang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins; Hanjun Jiang (A-SSCC, 2019)

A 1.2V 86dB SNDR 500kHz BW Linear-Exponential Multi-Bit Incremental ADC Using Positive Feedback in 65nm CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (A-SSCC, 2019)

A 550- $ mu$ W 20-kHz BW 100.8-dB SNDR Linear- Exponential Multi-Bit Incremental $ Sigma Delta$ ADC With 256 Clock Cycles in 65-nm CMOS. - Biao Wang; Sai-Weng Sin; Seng-Pan U; Franco Maloberti; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

Design of a High-Speed Time-Interleaved Sub-Ranging SAR ADC With Optimal Code Transfer Technique. - Dezhi Xing; Yan Zhu 001; Chi-Hang Chan; Franco Maloberti; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector. - Jianwei Liu 005; Chi-Hang Chan; Sai-Weng Sin; Seng-Pan U; Rui Paulo Martins (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A 17.7-pJ/Cycle ECG Processor for Arrhythmia Detection with High Immunity to Power Line Interference and Baseline Drift. - Yue Yin; Syed Muhammad Abubakar; Songyao Tan; Hanjun Jiang; Zhihua Wang 001; Seng-Pan U; Wen Jia (A-SSCC, 2020)

A 2.52 μΑ Wearable Single Lead Ternary Neural Network Based Cardiac Arrhythmia Detection Processor. - Syed Muhammad Abubakar; Yue Yin; Songyao Tan; Hanjun Jiang; Zhihua Wang 001; Seng-Pan U; Wen Jia (ISCAS, 2021)

SE5: Making a Career Choice. - Denis Daly; Zeynep Lulec; Rabia Tugce Yazicigil; Alison J. Burdett; Rituparna Mandal; Matheus Moreira; Dante G. Muratore; Aisha Walcott-Bryant; Ben Seng-Pan U (ISSCC, 2021)

A 2.63 μW ECG Processor With Adaptive Arrhythmia Detection and Data Compression for Implantable Cardiac Monitoring Device. - Yue Yin; Syed Muhammad Abubakar; Songyao Tan; Jiahua Shi; Peilin Yang; Wendi Yang; Hanjun Jiang; Zhihua Wang 001; Wen Jia; Seng-Pan U (IEEE Trans. Biomed. Circuits Syst., 2021)