Self Clock-Gating Scheme for Low Power Basic Logic Element Architecture. - R. Udaiyakumar; Senoj Joseph; T. V. P. Sundararajan; Dhasarathan Vigneswaran; R. Maheswar 001; Iraj S. Amiri (Wirel. Pers. Commun., 2018)

Performance Analysis in Digital Circuits for Process Corner Variations, Slew-Rate and Load Capacitance. - R. Udaiyakumar; Senoj Joseph; T. V. P. Sundararajan; Dhasarathan Vigneswaran; R. Maheswar 001; Iraj S. Amiri (Wirel. Pers. Commun., 2018)

Federated Transfer Learning for Authentication and Privacy Preservation Using Novel Supportive Twin Delayed DDPG (S-TD3) Algorithm for IIoT. - K. Arumugam; Srimathi J; Sudhanshu Maurya; Senoj Joseph; Anju Asokan; Poongodi M; Abdullah A. Algethami; Mounir Hamdi; Hafiz Tayyab Rauf (Sensors, 2021)