Alleviation of Data Timing Channels in Normalized/Subnormal Floating Point Multiplier. - Senthil Pitchai; VE. Jayanthi (J. Circuits Syst. Comput., 2021)

Design a Hybrid FPGA Architecture for Visible Digital Image Watermarking in Spatial and Frequency Domain. - VE. Jayanthi; Senthil Pitchai; M. Smitha (J. Circuits Syst. Comput., 2022)

Area-latency efficient floating point adder using interleaved alignment and normalization. - Senthil Pitchai; Saravanan Pitchai (Microprocess. Microsystems, 2023)