A 450-fs jitter PVT-robust fractional-resolution injection-locked clock multiplier using a DLL-based calibrator with replica-delay-cells. - Mina Kim; Seojin Choi; Jaehyouk Choi (VLSIC, 2015)

10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector. - Seojin Choi; Seyeon Yoo; Jaehyouk Choi (ISSCC, 2016)

A PVT-Robust and Low-Jitter Ring-VCO-Based Injection-Locked Clock Multiplier With a Continuous Frequency-Tracking Loop Using a Replica-Delay Cell and a Dual-Edge Phase Detector. - Seojin Choi; Seyeon Yoo; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2016)

A Low-Jitter and Fractional-Resolution Injection-Locked Clock Multiplier Using a DLL-Based Real-Time PVT Calibrator With Replica-Delay Cells. - Mina Kim; Seojin Choi; Taeho Seong; Jaehyouk Choi (IEEE J. Solid State Circuits, 2016)

19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (ISSCC, 2017)

Injection-locked frequency multiplier with a continuous frequency-tracking loop for 5G transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (ASP-DAC, 2018)

153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier. - Seojin Choi; Seyeon Yoo; Yongsun Lee; Yongwoo Jo; Jeonghyun Lee; Younghyun Lim; Jaehyouk Choi (VLSI Circuits, 2018)

A Low-Integrated-Phase-Noise 27-30-GHz Injection-Locked Frequency Multiplier With an Ultra-Low-Power Frequency-Tracking Loop for mm-Wave-Band 5G Transceivers. - Seyeon Yoo; Seojin Choi; Juyeop Kim; Heein Yoon; Yongsun Lee; Jaehyouk Choi (IEEE J. Solid State Circuits, 2018)

A 140fsrms-Jitter and -72dBc-Reference-Spur Ring-VCO-Based Injection-Locked Clock Multiplier Using a Background Triple-Point Frequency/Phase/Slope Calibrator. - Seyeon Yoo; Seojin Choi; Yongsun Lee; Taeho Seong; Younghyun Lim; Jaehyouk Choi (ISSCC, 2019)

An Ultra-Low-Jitter 22.8-GHz Ring-LC-Hybrid Injection-Locked Clock Multiplier With a Multiplication Factor of 114. - Seojin Choi; Seyeon Yoo; Yongsun Lee; Yongwoo Jo; Jeonghyun Lee; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2019)

A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency. - Jooeun Bang; Seojin Choi; Seyeon Yoo; Jeonghyun Lee; Juyeop Kim; Jaehyouk Choi (ESSCIRC, 2021)

32.4 A 104fsrms-Jitter and -61dBc-Fractional Spur 15GHz Fractional-N Subsampling PLL Using a Voltage-Domain Quantization-Error Cancelation Technique. - Juyeop Kim; Yongwoo Jo; Younghyun Lim; Taeho Seong; Hangi Park; Seyeon Yoo; Yongsun Lee; Seojin Choi; Jaehyouk Choi (ISSCC, 2021)

An 82fsrms-Jitter and 22.5mW-Power, 102GHz W-Band PLL Using a Power-Gating Injection-Locked Frequency-Multiplier- Based Phase Detector in 65nm CMOS. - Seyeon Yoo; Suneui Park; Seojin Choi; Yoonseo Cho; Heein Yoon; Chanwoong Hwang; Jaehyouk Choi (ISSCC, 2021)

A Low-Jitter and Low-Reference-Spur Ring-VCO- Based Injection-Locked Clock Multiplier Using a Triple-Point Background Calibrator. - Seyeon Yoo; Seojin Choi; Yongsun Lee; Taeho Seong; Younghyun Lim; Jaehyouk Choi (IEEE J. Solid State Circuits, 2021)

An Ultra-Low Jitter, Low-Power, 102-GHz PLL Using a Power-Gating Injection-Locked Frequency Multiplier-Based Phase Detector. - Suneui Park; Seojin Choi; Seyeon Yoo; Yoonseo Cho; Jaehyouk Choi (IEEE J. Solid State Circuits, 2022)