A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation. - Seok-Woo Choi; Hyun-Bae Lee; Hong-June Park (IEEE J. Solid State Circuits, 2006)

1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture. - Yongsam Moon; Yong-Ho Cho; Hyun-Bae Lee; Byung-Hoon Jeong; Seok-Hun Hyun; Byungchul Kim; In-Chul Jeong; Seong-Young Seo; Junho Shin; Seok-Woo Choi; Ho-Sung Song; Jung-Hwan Choi; et al. (ISSCC, 2009)