Slack redistribution for graceful degradation under voltage overscaling. - Andrew B. Kahng; Seokhyeong Kang; Rakesh Kumar 002; John Sartori (ASP-DAC, 2010)

Recovery-driven design: a power minimization methodology for error-tolerant processor modules. - Andrew B. Kahng; Seokhyeong Kang; Rakesh Kumar 002; John Sartori (DAC, 2010)

Designing a processor from the ground up to allow voltage/reliability tradeoffs. - Andrew B. Kahng; Seokhyeong Kang; Rakesh Kumar 002; John Sartori (HPCA, 2010)

Toward effective utilization of timing exceptions in design optimization. - Kwangok Jeong; Andrew B. Kahng; Seokhyeong Kang (ISQED, 2010)

Accuracy-configurable adder for approximate arithmetic designs. - Andrew B. Kahng; Seokhyeong Kang (DAC, 2012)

MAPG: Memory access power gating. - Kwangok Jeong; Andrew B. Kahng; Seokhyeong Kang; Tajana Simunic Rosing; Richard D. Strong (DATE, 2012)

Sensitivity-guided metaheuristics for accurate discrete gate sizing. - Jin Hu; Andrew B. Kahng; Seokhyeong Kang; Myung-Chul Kim; Igor L. Markov (ICCAD, 2012)

TAP: token-based adaptive power gating. - Andrew B. Kahng; Seokhyeong Kang; Tajana Rosing; Richard D. Strong (ISLPED, 2012)

Construction of realistic gate sizing benchmarks with known optimal solutions. - Andrew B. Kahng; Seokhyeong Kang (ISPD, 2012)

Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors. - Andrew B. Kahng; Seokhyeong Kang; Rakesh Kumar 002; John Sartori (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Smart non-default routing for clock power reduction. - Andrew B. Kahng; Seokhyeong Kang; Hyein Lee 001 (DAC, 2013)

Active-mode leakage reduction with data-retained power gating. - Andrew B. Kahng; Seokhyeong Kang; Bongil Park (DATE, 2013)

High-performance gate sizing with a signoff timer. - Andrew B. Kahng; Seokhyeong Kang; Hyein Lee 001; Igor L. Markov; Pankit Thapar (ICCAD, 2013)

Statistical analysis and modeling for error composition in approximate computation circuits. - Wei-Ting Jonas Chan; Andrew B. Kahng; Seokhyeong Kang; Rakesh Kumar 002; John Sartori (ICCD, 2013)

Learning-based approximation of interconnect delay and slew in signoff timing tools. - Andrew B. Kahng; Seokhyeong Kang; Hyein Lee 001; Siddhartha Nath; Jyoti Wadhwani (SLIP, 2013)

Many-Core Token-Based Adaptive Power Gating. - Andrew B. Kahng; Seokhyeong Kang; Tajana Simunic Rosing; Richard D. Strong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Enhancing the Efficiency of Energy-Constrained DVFS Designs. - Andrew B. Kahng; Seokhyeong Kang; Rakesh Kumar 002; John Sartori (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Low-Power Integrated-Circuit Implementation Exploiting System and Application Information / - Seokhyeong Kang (2013)

A new methodology for reduced cost of resilience. - Andrew B. Kahng; Seokhyeong Kang; Jiajia Li 002 (ACM Great Lakes Symposium on VLSI, 2014)

An optimal operating point by using error monitoring circuits with an error-resilient technique. - Jaemin Lee; Seungwon Kim; Youngmin Kim; Seokhyeong Kang (VLSI-SoC, 2015)

An Improved Methodology for Resilient Design Implementation. - Andrew B. Kahng; Seokhyeong Kang; Jiajia Li 002; José Pineda de Gyvez (ACM Trans. Design Autom. Electr. Syst., 2015)

Novel approximate synthesis flow for energy-efficient FIR filter. - Yesung Kang; Jaewoo Kim; Seokhyeong Kang (ICCD, 2016)

Skew control methodology for useful-skew implementation. - SangGi Do; Seungwon Kim; Seokhyeong Kang (ISOCC, 2016)

Wakeup scheduling and its buffered tree synthesis for power gating circuits. - Sangmin Kim; Seungwhun Paik; Seokhyeong Kang; Youngsoo Shin (Integr., 2016)

Novel Adaptive Power-Gating Strategy and Tapered TSV Structure in Multilayer 3D IC. - Seungwon Kim; Seokhyeong Kang; Ki Jin Han; Youngmin Kim (ACM Trans. Design Autom. Electr. Syst., 2016)

Synthesis of Dual-Mode Circuits Through Library Design, Gate Sizing, and Clock-Tree Optimization. - Sangmin Kim; Seokhyeong Kang; Youngsoo Shin (ACM Trans. Design Autom. Electr. Syst., 2016)

Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization. - Seungwon Kim; SangGi Do; Seokhyeong Kang (DAC, 2017)

GRASP based metaheuristics for layout pattern classification. - Mingyu Woo; Seungwon Kim; Seokhyeong Kang (ICCAD, 2017)

A Novel Ternary Multiplier Based on Ternary CMOS Compact Model. - Yesung Kang; Jaewoo Kim; Sunmin Kim; Sunhae Shin; E-San Jang; Jae Won Jeong; Kyung Rok Kim; Seokhyeong Kang (ISMVL, 2017)

An optimal gate design for the synthesis of ternary logic circuits. - Sunmean Kim; Taeho Lim; Seokhyeong Kang (ASP-DAC, 2018)

Fast chip-package-PCB coanalysis methodology for power integrity of multi-domain high-speed memory: A case study. - Seungwon Kim; Ki Jin Han; Youngmin Kim; Seokhyeong Kang (DATE, 2018)

Estimation of Leakage Distribution Utilizing Gaussian Mixture Model. - Hyun-jeong Kwon; Young Hwan Kim; Seokhyeong Kang (ISOCC, 2018)

SoftCorner: Relaxation of Corner Values for Deterministic Static Timing Analysis of VLSI Systems. - Hyun-jeong Kwon; Jae Hoon Kim; Seokhyeong Kang; Young Hwan Kim (IEEE Access, 2018)

Statistical Leakage Analysis Using Gaussian Mixture Model. - Hyun-jeong Kwon; Mingyu Woo; Young Hwan Kim; Seokhyeong Kang (IEEE Access, 2018)

Power Delivery Pathfinding for Emerging Die-to-Wafer Integration Technology. - Andrew B. Kahng; Seokhyeong Kang; Seungwon Kim; Kambiz Samadi; Bangqi Xu (DATE, 2019)

Fence-Region-Aware Mixed-Height Standard Cell Legalization. - SangGi Do; Mingyu Woo; Seokhyeong Kang (ACM Great Lakes Symposium on VLSI, 2019)

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic. - Sunmean Kim; Sung-Yun Lee; Sunghye Park; Seokhyeong Kang (ISMVL, 2019)

Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm. - Sung-Yun Lee; Sunmean Kim; Seokhyeong Kang (ISMVL, 2019)

Outlier-aware Time-multiplexing MAC for Higher Energy-Efficiency on CNNs. - Eunji Kwon; Yesung Kang; Seokhyeong Kang (ISOCC, 2019)

Multi-Threshold Voltages Graphene Barristor-Based Ternary ALU. - Sunghye Park; Sunmean Kim; Seokhyeong Kang (ISOCC, 2019)

Power Integrity Coanalysis Methodology for Multi-Domain High-Speed Memory Systems. - Seungwon Kim; Ki Jin Han; Youngmin Kim; Seokhyeong Kang (IEEE Access, 2019)

SmartGrid: Video Retargeting With Spatiotemporal Grid Optimization. - Ho Sub Lee; Gyu Jin Bae; Sung In Cho; Young Hwan Kim; Seokhyeong Kang (IEEE Access, 2019)

Late Breaking Results: Reinforcement Learning-based Power Management Policy for Mobile Device Systems. - Eunji Kwon; Sodam Han; Yoonho Park; Young Hwan Kim; Seokhyeong Kang (DAC, 2020)

Analysis and Solution of CNN Accuracy Reduction over Channel Loop Tiling. - Yesung Kang; Yoonho Park; Sunghoon Kim; Eunji Kwon; Taeho Lim; Sangyun Oh; Mingyu Woo; Seokhyeong Kang (DATE, 2020)

GRLC: grid-based run-length compression for energy-efficient CNN accelerator. - Yoonho Park; Yesung Kang; Sunghoon Kim; Eunji Kwon; Seokhyeong Kang (ISLPED, 2020)

Extreme Low Power Technology using Ternary Arithmetic Logic Circuits via Drastic Interconnect Length Reduction. - Kiyung Kim; Sunmean Kim; Yongsu Lee; Daeyeon Kim; So-Young Kim; Seokhyeong Kang; Byoung Hun Lee (ISMVL, 2020)

MTCMOS-based Ternary to Binary Converter. - Seunghan Baek; Sunmean Kim; Youngchang Choi; Seokhyeong Kang (ISOCC, 2020)

Low-Power 4-Trit Current-Steering DAC for Ternary Data Conversion. - Youngchang Choi; Sunmean Kim; Seunghan Baek; Seokhyeong Kang (ISOCC, 2020)

Proactive Scenario Characteristic-Aware Online Power Management on Mobile Systems. - Sodam Han; Yonghee Yun; Young Hwan Kim; Seokhyeong Kang (IEEE Access, 2020)

Compact Topology-Aware Bus Routing for Design Regularity. - Daeyeon Kim; SangGi Do; Sung-Yun Lee; Seokhyeong Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Additive Statistical Leakage Analysis Using Exponential Mixture Model. - Hyun-jeong Kwon; Sung-Yun Lee; Young Hwan Kim; Seokhyeong Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits. - Sunmean Kim; Sung-Yun Lee; Sunghye Park; Kyung Rok Kim; Seokhyeong Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Approach to Improve the Performance Using Bit-level Sparsity in Neural Networks. - Yesung Kang; Eunji Kwon; Seunggyu Lee; Younghoon Byun; Youngjoo Lee; Seokhyeong Kang (DATE, 2021)

MDARTS: Multi-objective Differentiable Neural Architecture Search. - Sunghoon Kim; Hyun-jeong Kwon; Eunji Kwon; Youngchang Choi; Tae-Hyun Oh; Seokhyeong Kang (DATE, 2021)

Machine Learning Framework for Early Routability Prediction with Artificial Netlist Generator. - Daeyeon Kim; Hyun-jeong Kwon; Sung-Yun Lee; Seungwon Kim; Mingyu Woo; Seokhyeong Kang (DATE, 2021)

Design and Analysis of a Low-Power Ternary SRAM. - Youngchang Choi; Sunmean Kim; Kyongsu Lee; Seokhyeong Kang (ISCAS, 2021)

Ternary Sense Amplifier Design for Ternary SRAM. - Minjeong Choi; Youngchang Choi; Sunmean Kim; Seokhyeong Kang (ISOCC, 2021)

Comparative Analysis between Verilog and Chisel in RISC-V Core Design and Verification. - Jaekyung Im; Seokhyeong Kang (ISOCC, 2021)

Data Protection Method for Flash Memory in Serial Peripheral Interface. - Aeri Kim; Seokhyeong Kang (ISOCC, 2021)

Components Analysis on Audio Signal Mixtures. - Chanhee Lee; Sangho Yoon; Seokhyeong Kang (ISOCC, 2021)

Giga-sample Data Acquisition Method for High-speed DDR5 SDRAM. - Seunggyu Lee; Jongho Yoon 001; Jakang Lee; Seokhyeong Kang (ISOCC, 2021)

Memcapacitor based Minimum and Maximum Gate Design. - Jiyoung Min; Sunmean Kim; Seokhyeong Kang (ISOCC, 2021)

A 5.5mW/Channel 2-to-7 GHz Frequency Synthesizable Qubit-Controlling Cryogenic Pulse Modulator for Scalable Quantum Computers. - Kiseo Kang; ByungJun Kim; Gahyun Choi; Sun-Kyung Lee 002; Jisoo Choi; Jaeho Lee; Seokhyeong Kang; Moonjoo Lee; Ho-Jin Song; Yonuk Chong; Jae-Yoon Sim (VLSI Circuits, 2021)

Fluctuation-Based Fade Detection for Local Scene Changes. - Sangho Yoon; Chanhee Lee; Ho Sub Lee; Young Hwan Kim; Seokhyeong Kang (IEEE Access, 2021)

Reinforcement Learning-Based Power Management Policy for Mobile Device Systems. - Eunji Kwon; Sodam Han; Yoonho Park; Jongho Yoon 001; Seokhyeong Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Variation-Aware SRAM Cell Optimization Using Deep Neural Network-Based Sensitivity Analysis. - Hyun-jeong Kwon; Daeyeon Kim; Young Hwan Kim; Seokhyeong Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Low-Power Ternary Multiplication Using Approximate Computing. - Sunmean Kim; Yesung Kang; Seunghan Baek; Youngchang Choi; Seokhyeong Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology. - Andrew B. Kahng; Seokhyeong Kang; Seungwon Kim; Bangqi Xu (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Adaptive FSP: Adaptive Architecture Search with Filter Shape Pruning. - Aeri Kim; Seungju Lee; Eunji Kwon; Seokhyeong Kang (ACCV (1), 2022)

Signal-Integrity-Aware Interposer Bus Routing in 2.5D Heterogeneous Integration. - Sung-Yun Lee; Daeyeon Kim; Kyungjun Min; Seokhyeong Kang (ASP-DAC, 2022)

A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computers. - Sunghye Park; Daeyeon Kim; Minhyuk Kweon; Jae-Yoon Sim; Seokhyeong Kang (DAC, 2022)

Design and Evaluation Frameworks for Advanced RISC-based Ternary Processor. - Dongyun Kam; Jung Gyu Min; Jongho Yoon 001; Sunmean Kim; Seokhyeong Kang; Youngjoo Lee (DATE, 2022)

GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN. - Myong Kong; Daeyeon Kim; Minhyuk Kweon; Seokhyeong Kang (ACM Great Lakes Symposium on VLSI, 2022)

MCQA: Multi-Constraint Qubit Allocation for Near-FTQC Device. - Sunghye Park; Dohun Kim; Jae-Yoon Sim; Seokhyeong Kang (ICCAD, 2022)

CPR: Crossbar-grain Pruning for an RRAM-based Accelerator with Coordinate-based Weight Mapping. - Jihye Park; Seokhyeong Kang (ICCD, 2022)

A Cryo-CMOS Controller IC With Fully Integrated Frequency Generators for Superconducting Qubits. - Kiseo Kang; Donggyu Minn; Seunghun Bae; Jaeho Lee; Seongun Bae; Gichang Jung; Seokhyeong Kang; Moonjoo Lee; Ho-Jin Song; Jae-Yoon Sim (ISSCC, 2022)

A 40-nm Cryo-CMOS Quantum Controller IC for Superconducting Qubit. - Kiseo Kang; Donggyu Minn; Seongun Bae; Jaeho Lee; Seokhyeong Kang; Moonjoo Lee; Ho-Jin Song; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2022)

Lightweight Speaker Recognition in Poincaré Spaces. - Jieun Lee; Kim Sung-Bin; Seokhyeong Kang; Tae-Hyun Oh (IEEE Signal Process. Lett., 2022)

CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration. - Hyeokjun Kwon; Younghoon Byun; Seokhyeong Kang; Youngjoo Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Graph Partitioning Approach for Fast Quantum Circuit Simulation. - Jaekyung Im; Seokhyeong Kang (ASP-DAC, 2023)

Reinforcement Learning-based Analog Circuit Optimizer using gm/ID for Sizing. - Minjeong Choi; Youngchang Choi; Kyongsu Lee; Seokhyeong Kang (DAC, 2023)

MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-Actors. - Youngchang Choi; Minjeong Choi; Kyongsu Lee; Seokhyeong Kang (DATE, 2023)

Routability Prediction using Deep Hierarchical Classification and Regression. - Daeyeon Kim; Jakang Lee; Seokhyeong Kang (DATE, 2023)

Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer Vision. - Eunji Kwon; Haena Song; Jihye Park; Seokhyeong Kang (DATE, 2023)

RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization. - Sung-Yun Lee; Seonghyeon Park; Daeyeon Kim; Minjae Kim; Tuyen Pham Le 001; Seokhyeong Kang (DATE, 2023)

FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural Networks. - Haena Song; Jongho Yoon 001; Dohun Kim; Eunji Kwon; Tae-Hyun Oh; Seokhyeong Kang (DATE, 2023)

ClusterNet: Routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks. - Kyungjun Min; Seongbin Kwon; Sung-Yun Lee; Dohun Kim; Sunghye Park; Seokhyeong Kang (ICCAD, 2023)

Routability Prediction and Optimization Using Explainable AI. - Seonghyeon Park; Daeyeon Kim; Seongbin Kwon; Seokhyeong Kang (ICCAD, 2023)

Multi-Source Transfer Learning for Design Technology Co-Optimization. - Jakang Lee; Jaeseung Lee; Seonghyeon Park; Seokhyeong Kang (ISLPED, 2023)

Placement Initialization via Community Detection. - Junseok Hur; Jaekyung Im; Seokhyeong Kang (ISOCC, 2023)

Advanced Parasitic Capacitance Extraction using Active Learning. - Donggyu Kim; Jakang Lee; Seokhyeong Kang (ISOCC, 2023)

Soft Actor-Critic Reinforcement Learning-Based Optimization for Analog Circuit Sizing. - Sejin Park 001; Youngchang Choi; Seokhyeong Kang (ISOCC, 2023)

Machine Learning-based Fast Circuit Simulation for Analog Circuit Array. - Jaeseung Lee; Sejin Park 001; Minhyeok Kweon; Seokhyeong Kang (MLCAD, 2023)

Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization. - Seonghyeon Park; Daeyeon Kim; Seokhyeong Kang (SLIP, 2023)

Hybrid Circuit Mapping: Leveraging the Full Spectrum of Computational Capabilities of Neutral Atom Quantum Computers. - Ludwig Schmid; Sunghye Park; Seokhyeong Kang; Robert Wille (CoRR, 2023)

Optimizing Ternary Multiplier Design With Fast Ternary Adder. - Jongho Yoon 001; Seunghan Baek; Sunmean Kim; Seokhyeong Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Construction of Realistic Place-and-Route Benchmarks for Machine Learning Applications. - Daeyeon Kim; Sung-Yun Lee; Kyungjun Min; Seokhyeong Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

SkyPlace: A New Mixed-size Placement Framework using Modularity-based Clustering and SDP Relaxation. - Jaekyung Im; Seokhyeong Kang (DAC, 2024)

PPA-Relevant Clustering-Driven Placement for Large-Scale VLSI Designs. - Andrew B. Kahng; Seokhyeong Kang; Sayak Kundu; Kyungjun Min; Seonghyeon Park; Bodhisatta Pramanik (DAC, 2024)

RL-PTQ: RL-based Mixed Precision Quantization for Hybrid Vision Transformers. - Eunji Kwon; Minxuan Zhou; Weihong Xu; Tajana Rosing; Seokhyeong Kang (DAC, 2024)

HiLight: A Comprehensive Framework for High-Performance and Lightweight Scalability in Surface Code Communication. - Sunghye Park; Dohun Kim; Seokhyeong Kang (DAC, 2024)

Improvement of Mixed Track - Height Standard-Cell Placement. - Andrew B. Kahng; Seokhyeong Kang; Minhyuk Kweon (DATE, 2024)

ViT- ToGo: Vision Transformer Accelerator with Grouped Token Pruning. - Seungju Lee; Kyumin Cho; Eunji Kwon; Sejin Park 001; Seojeong Kim; Seokhyeong Kang (DATE, 2024)

Trans-Net: Knowledge-Transferring Analog Circuit Optimizer with a Netlist-Based Circuit Representation. - Ho-Jin Lee; Kyeong-Jun Lee; Youngchang Choi; Kyongsu Lee; Seokhyeong Kang; Jae-Yoon Sim (DATE, 2024)

CTRL-B: Back-End-Of-Line Configuration Pathfinding Using Cross-Technology Transferable Reinforcement Learning. - Sung-Yun Lee; Kyungjun Min; Seokhyeong Kang (DATE, 2024)

Unveiling the Black-Box: Leveraging Explainable AI for FPGA Design Space Optimization. - Jaemin Seo; Sejin Park 001; Seokhyeong Kang (DATE, 2024)

RL-Fill: Timing-Aware Fill Insertion using Reinforcement Learning. - Jinoh Cho; Seonghyeon Park; Jakang Lee; Sung-Yun Lee; Jinmo Ahn; Seokhyeong Kang (ICCAD, 2024)

Improving Timing & Power Trade-off in Post-place Optimization Using Multi-agent Reinforcement Learning. - Jaemin Seo; Sejin Park 001; Seokhyeong Kang (ICCAD, 2024)

QNSA: Quantum Neural Simulated Annealing for Combinatorial Optimization. - Seongbin Kwon; Dohun Kim; Sunghye Park; Seojeong Kim; Seokhyeong Kang (ISQED, 2024)

TA3D: Timing-Aware 3D IC Partitioning and Placement by Optimizing the Critical Path. - Donggyu Kim; Minjae Kim; Junseok Hur; Jakang Lee; Jinoh Cho; Seokhyeong Kang (MLCAD, 2024)

MA-Opt: Reinforcement Learning-Based Analog Circuit Optimization Using Multi-Actors. - Youngchang Choi; Sejin Park 001; Minjeong Choi; Kyongsu Lee; Seokhyeong Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Mobile Transformer Accelerator Exploiting Various Line Sparsity and Tile-Based Dynamic Quantization. - Eunji Kwon; Jongho Yoon 001; Seokhyeong Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Leveraging Machine Learning Techniques for Traditional EDA Workflow Enhancement. - Jinoh Cho; Jaekyung Im; Jaeseung Lee; Kyungjun Min; Seonghyeon Park; Jaemin Seo; Jongho Yoon 001; Seokhyeong Kang (ASP-DAC, 2025)

PC-Opt: Partition and Conquest-based Optimizer using Multi-Agents for Complex Analog Circuits. - Youngchang Choi; Sejin Park 001; Ho-Jin Lee; Kyongsu Lee; Jae-Yoon Sim; Seokhyeong Kang (ASP-DAC, 2025)

LIBMixer: An all-MLP Architecture for Cell Library Characterization towards Design Space Optimization. - Jaeseung Lee; Sunggyu Jang; Jakang Lee; Seokhyeong Kang (ASP-DAC, 2025)

ParaFormer: A Hybrid Graph Neural Network and Transformer Approach for Pre-Routing Parasitic RC Prediction. - Jongho Yoon 001; Jakang Lee; Donggyu Kim; Junseok Hur; Seokhyeong Kang (ASP-DAC, 2025)

Neural Circuit Parameter Prediction for Efficient Quantum Data Loading. - Dohun Kim; Sunghye Park; Seokhyeong Kang (DATE, 2025)

Improving LLM-Based Verilog Code Generation with Data Augmentation and RL. - Kyungjun Min; Seonghyeon Park; Hyeonwoo Park; Jinoh Cho; Seokhyeong Kang (DATE, 2025)

Invited: Artificial Netlist Generation for Enhanced Circuit Data Augmentation. - Seokhyeong Kang (ISPD, 2025)