Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. - Yong-Ha Park; Seon-Ho Han; Hoi-Jun Yoo (ASP-DAC, 2001)

A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system. - Yong-Ha Park; Seon-Ho Han; Junghwan Lee; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2001)

An 800-MHz low-power direct digital frequency synthesizer with an on-chip D/a converter. - Byung-Do Yang; Jang-Hong Choi; Seon-Ho Han; Lee-Sup Kim; Hyun-Kyu Yu (IEEE J. Solid State Circuits, 2004)