A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate. - Seon-Kyoo Lee; Young-Sang Kim; Hyunsoo Ha; Young Hun Seo; Hong-June Park; Jae-Yoon Sim (ISSCC, 2009)

A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS. - Seon-Kyoo Lee; Young Hun Seo; Yunjae Suh; Hong-June Park; Jae-Yoon Sim (ISSCC, 2010)

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS. - Seon-Kyoo Lee; Young Hun Seo; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2010)

A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition. - Seon-Kyoo Lee; Young-Sang Kim; Hong-June Park; Jae-Yoon Sim (J. Electr. Comput. Eng., 2011)

A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. - Young-Sang Kim; Seon-Kyoo Lee; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2011)

A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface. - Seon-Kyoo Lee; Seung-Jin Park; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2011)

A 1-GHz Digital PLL With a 3-ps Resolution Floating-Point-Number TDC in a 0.18-μm CMOS. - Young Hun Seo; Seon-Kyoo Lee; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling. - Hyunsoo Ha; Yunjae Suh; Seon-Kyoo Lee; Hong-June Park; Jae-Yoon Sim (CICC, 2012)

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. - Young-Sik Kim; Seon-Kyoo Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Bae Lee; Joo-Sun Choi; Hong-June Park; Jae-Yoon Sim (ISSCC, 2012)

A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation. - Seon-Kyoo Lee; Hyunsoo Ha; Hong-June Park; Jae-Yoon Sim (ISSCC, 2012)

A 95fJ/b current-mode transceiver for 10mm on-chip interconnect. - Seon-Kyoo Lee; Seung-Hun Lee; Dennis Sylvester; David T. Blaauw; Jae-Yoon Sim (ISSCC, 2013)

A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation. - Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2013)

A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface. - Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Current-Mode Transceiver for Silicon Interposer Channel. - Seung-Hun Lee; Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE J. Solid State Circuits, 2014)

A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation. - Hyunsoo Ha; Seon-Kyoo Lee; Byungsub Kim; Hong-June Park; Jae-Yoon Sim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip. - Hyun-Jin Kim; Jeong-Don Lim; Jang-Woo Lee; Dae-Hoon Na; Joon-Ho Shin; Chae-Hoon Kim; Seungwoo Yu; Ji-Yeon Shin; Seon-Kyoo Lee; Devraj Rajagopal; Sang-Tae Kim; Kyeong-Tae Kang; et al. (ISSCC, 2015)

7.5 A 128Gb 2b/cell NAND flash memory in 14nm technology with tPROG=640µs and 800MB/s I/O rate. - Seungjae Lee 001; Jin-Yub Lee; Il-Han Park; Jong-Yeol Park; Sung-Won Yun; Minsu Kim 004; Jong-Hoon Lee; Min-Seok Kim; Kangbin Lee; Taeeun Kim; Byungkyu Cho; Dooho Cho; et al. (ISSCC, 2016)

A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. - Jang-Woo Lee; Dae-Hoon Na; Anil Kavala; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Tongsung Kim; Seon-Kyoo Lee; Dong-Su Jang; Byung-Kwan Chun; Youngmin Jo; et al. (VLSI Circuits, 2020)

Issues and Key Technologies for Next Generation 3D NAND. - Chiweon Yoon; Hyunggon Kim; Seon-Kyoo Lee; Jinyub Lee; Jai Hyuk Song (ICEIC, 2021)

A 1.8-Gb/s/Pin 16-Tb NAND Flash Memory Multi-Chip Package With F-Chip for High-Performance and High-Capacity Storage. - Dae-Hoon Na; Jang-Woo Lee; Seon-Kyoo Lee; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Anil Kavala; Tongsung Kim; Dong-Su Jang; Youngmin Jo; Ji-Yeon Shin; et al. (IEEE J. Solid State Circuits, 2021)

A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect. - Jaeho Lee; Kyongsu Lee; Jae-Yoon Sim; Seon-Kyoo Lee (VLSI Technology and Circuits, 2024)

A $94 text{fs}_{ text{rms}}$-Jitter and -249.3dB FoM 4.0GHz Ring-Oscillator-Based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch. - Dongjun Park; Heesung Roh; Seon-Kyoo Lee; Jae-Yoon Sim (VLSI Technology and Circuits, 2024)