Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign. - Seong-I Lei; Wai-Kei Mak (FPL, 2011)

Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design. - Seong-I Lei; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Double patterning-aware detailed routing with mask usage balancing. - Seong-I Lei; Chris Chu; Wai-Kei Mak (ISQED, 2014)

Minimum implant area-aware placement and threshold voltage refinement. - Seong-I Lei; Wai-Kei Mak; Chris Chu (ASP-DAC, 2016)

Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs. - Seong-I Lei; Wai-Kei Mak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Minimum Implant Area-Aware Placement and Threshold Voltage Refinement. - Wai-Kei Mak; Wan-Sin Kuo; Shi-Han Zhang; Seong-I Lei; Chris Chu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)