Parallel dynamic logic (PDL) with speed-enhanced skewed static (SSS) logic. - Chulwoo Kim; Seong-Ook Jung; Kwang-Hyun Baek; Sung-Mo Kang (ISCAS, 2000)

Noise-aware power optimization for on-chip interconnect. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (ISLPED, 2000)

Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. - Ki-Wook Kim; Seong-Ook Jung; Prashant Saxena; C. L. Liu 001; Sung-Mo Kang (DAC, 2001)

Transistor sizing for reliable domino logic design in dual threshold voltage technologies. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (ACM Great Lakes Symposium on VLSI, 2001)

2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. - Seung-Moon Yoo; Seong-Ook Jung; Sung-Mo Kang (ACM Great Lakes Symposium on VLSI, 2001)

Noise constrained power optimization for dual VT domino logic. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (ISCAS (4), 2001)

Skew-tolerant high-speed (STHS) domino logic. - Seong-Ook Jung; Seung-Moon Yoo; Ki-Wook Kim; Sung-Mo Kang (ISCAS (4), 2001)

Coupling-aware minimum delay optimization for domino logic circuits. - Ki-Wook Kim; Seong-Ook Jung; Sung-Mo Kang (ISCAS (5), 2001)

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. - Seung-Moon Yoo; Seong-Ook Jung; Sung-Mo Kang (ISCAS (4), 2001)

New current-mode sense amplifiers for high density DRAM and PIM architectures. - Seung-Moon Yoo; Chulwoo Kim; Seong-Ook Jung; Kwang-Hyun Baek; Sung-Mo Kang (ISCAS (4), 2001)

Low-swing clock domino logic incorporating dual supply and dual threshold voltages. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (DAC, 2002)

Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (DATE, 2002)

Optimal Timing for Skew-Tolerant High-Speed Domino Logic. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (ISVLSI, 2002)

Noise constrained transistor sizing and power optimization for dual Vst domino logic. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology - Seong-Ook Jung (2002)

Timing constraints for domino logic gates with timing-dependent keepers. - Seong-Ook Jung; Ki-Wook Kim; Sung-Mo Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Minimum delay optimization for domino circuits - a coupling-aware approach. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Sung-Mo Kang (ACM Trans. Design Autom. Electr. Syst., 2003)

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. - Ki-Wook Kim; Seong-Ook Jung; Taewhan Kim 001; Prashant Saxena; C. L. Liu 001; S.-M. S. Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Noise-aware interconnect power optimization in domino logic synthesis. - Ki-Wook Kim; Seong-Ook Jung; Unni Narayanan; C. L. Liu 001; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic. - Ge Yang 004; Seong-Ook Jung; Kwang-Hyun Baek; Soo Hwan Kim; Suki Kim; Sung-Mo Kang (ISCAS (2), 2004)

A 32-bit carry lookahead adder using dual-path all-N logic. - Ge Yang 004; Seong-Ook Jung; Kwang-Hyun Baek; Soo Hwan Kim; Suki Kim; Sung-Mo Kang (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Thyristor-Based Volatile Memory in Nano-Scale CMOS. - Rich Roy; Farid Nemati; Ken Young; Bruce Bateman; Rajesh Chopra; Seong-Ook Jung; Chiming Show; Hyun-Jin Cho (ISSCC, 2006)

Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates. - Myeong-Eun Hwang; Seong-Ook Jung; Kaushik Roy 001 (ISLPED, 2007)

Race-Free Mixed Serial-Parallel Comparison for Low Power Content Addressable Memory. - Seong-Ook Jung; Sei-Seung Yoon (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Numerical Estimation of Yield in Sub-100-nm SRAM Design Using Monte Carlo Simulation. - Hyunwoo Nho; Sei-Seung Yoon; S. Simon Wong; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

Serial-Parallel Content Addressable Memory with a Conditional Driver (SPCwCD). - Mingu Kang; Seong-Ook Jung (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. - Myeong-Eun Hwang; Seong-Ook Jung; Kaushik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Process variation tolerant all-digital multiphase DLL for DDR3 interface. - Heechai Kang; Kyungho Ryu; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (CICC, 2010)

Design Methodologies for STT-MRAM (Spin-Torque Transfer Magnetic Random Access Memory) Sensing Circuits. - Jisu Kim; Jee-Hwan Song; Seung-Hyuk Kang; Sei-Seung Yoon; Seong-Ook Jung (IEICE Trans. Electron., 2010)

A 90° phase-shift DLL with closed-loop DCC for high-speed mobile DRAM interface. - Dong-Hoon Jung; Kyungho Ryu; Seong-Ook Jung (IEEE Trans. Consumer Electron., 2010)

A DLL based clock generator for low-power mobile SoCs. - Kyungho Ryu; Dong Hun Jung; Seong-Ook Jung (IEEE Trans. Consumer Electron., 2010)

MTJ based non-volatile flip-flop in deep submicron technology. - Youngdon Jung; Jisu Kim; Kyungho Ryu; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISOCC, 2011)

Sensing margin trend with technology scaling in MRAM. - Jee-Hwan Song; Jisu Kim; Seung-Hyuk Kang; Sei-Seung Yoon; Seong-Ook Jung (Int. J. Circuit Theory Appl., 2011)

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (ESSCIRC, 2012)

Static read stability and write ability metrics in FinFET based SRAM considering read and write-assist circuits. - Hanwool Jeong; Younghwi Yang; Junha Lee; Jisu Kim; Seong-Ook Jung (ICECS, 2012)

Impact of fin thickness and height on read stability / write ability in tri-gate FinFET based SRAM. - Junha Lee; Hanwool Jeong; Younghwi Yang; Jisu Kim; Seong-Ook Jung (ISOCC, 2012)

Integration of dual channel timing formatter system for high speed memory test equipment. - Jaeseok Park; Ingeol Lee; Young-Seok Park; Sung-Geun Kim; Kyungho Ryu; Dong-Hoon Jung; Kangwook Jo; Choong Keun Lee; Hongil Yoon; Seong-Ook Jung; Woo-Young Choi; Sungho Kang 001 (ISOCC, 2012)

Process Variation Tolerant All-Digital 90° Phase Shift DLL for DDR3 Interface. - Heechai Kang; Kyungho Ryu; Dong-Hoon Jung; Donghwan Lee; Won Lee; SuHo Kim; JongRyun Choi; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A DLL With Dual Edge Triggered Phase Detector for Fast Lock and Low Jitter Clock Generator. - Kyungho Ryu; Dong-Hoon Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM). - Jisu Kim; Kyungho Ryu; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A Magnetic Tunnel Junction Based Zero Standby Leakage Current Retention Flip-Flop. - Kyungho Ryu; Jisu Kim; Jiwan Jung; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2012)

All-digital 90° phase-shift DLL with a dithering jitter suppression scheme. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Won Lee; Seong-Ook Jung (CICC, 2013)

All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate. - Kyungho Ryu; Dong-Hoon Jung; Seong-Ook Jung (ESSCIRC, 2013)

A 0.67nJ/S time-domain temperature sensor for low power on-chip thermal management. - Young-Jae An; Kyungho Ryu; Dong-Hoon Jung; Seung-Han Woo; Seong-Ook Jung (ICCE, 2013)

A comparative study of STT-MTJ based non-volatile flip-flops. - Taehui Na; Kyungho Ryu; Jisu Kim; Seung-Hyuk Kang; Seong-Ook Jung (ISCAS, 2013)

Dynamic mixed serial-parallel content addressable memory (DMSP CAM). - Mingu Kang; Jisu Kim; Younghwi Yang; Seong-Ook Jung (Int. J. Circuit Theory Appl., 2013)

ADDLL for Clock-Deskew Buffer in High-Performance SoCs. - Jung-Hyun Park; Dong-Hoon Jung; Kyungho Ryu; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Pseudo NMOS based sense amplifier for high speed single-ended SRAM. - Hanwool Jeong; Taewon Kim; Seong-Ook Jung; Taejoong Song; Gyu-Hong Kim (ICECS, 2014)

High-performance low-power magnetic tunnel junction based non-volatile flip-flop. - Taehui Na; Kyungho Ryu; Jisu Kim; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISCAS, 2014)

An MTJ-based non-volatile flip-flop for high-performance SoC. - Youngdon Jung; Jisu Kim; Kyungho Ryu; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (Int. J. Circuit Theory Appl., 2014)

A Split-Path Sensing Circuit for Spin Torque Transfer MRAM. - Jisu Kim; Taehui Na; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Reference-Scheme Study and Novel Reference Scheme for Deep Submicrometer STT-RAM. - Taehui Na; Jisu Kim; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector. - Kyungho Ryu; Dong-Hoon Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

One-Sided Static Noise Margin and Gaussian-Tail-Fitting Method for SRAM. - Hanwool Jeong; Younghwi Yang; Junha Lee; Jisu Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2014)

STT-MRAM Sensing Circuit With Self-Body Biasing in Deep Submicron Technologies. - Jisu Kim; Kyungho Ryu; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2014)

An Offset-Canceling Triple-Stage Sensing Circuit for Deep Submicrometer STT-RAM. - Taehui Na; Jisu Kim; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Comparative Study of Various Latch-Type Sense Amplifiers. - Taehui Na; Seung-Han Woo; Jisu Kim; Hanwool Jeong; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Efficiency analysis of importance sampling in deep submicron STT-RAM design using uncontrollable industry-compatible model parameter. - Taehui Na; Hanwool Jeong; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ICECS, 2015)

Reference-circuit analysis for high-bandwidth spin transfer torque random access memory. - Byungkyu Song; Taehui Na; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISLPED, 2015)

Low power SRAM design for 14 nm GAA Si-nanowire technology. - Gaurav Kaushal; H. Jeong; Satish Maheshwaram; S. K. Manhas; Sudeb Dasgupta; Seong-Ook Jung (Microelectron. J., 2015)

Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM. - Hanwool Jeong; Taewon Kim; Kyoman Kang; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM. - Hanwool Jeong; Taewon Kim; Younghwi Yang; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

All-Digital Fast-Locking Delay-Locked Loop Using a Cyclic-Locking Loop for DRAM. - Dong-Hoon Jung; Young-Jae An; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Temperature-Tracking Sensing Scheme With Adaptive Precharge and Noise Compensation Scheme in PRAM. - Junyoung Ko; Jisu Kim; Youngdon Choi; Hyun Kook Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory. - Taehui Na; Jisu Kim; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Latch Offset Cancellation Sense Amplifier for Deep Submicrometer STT-RAM. - Byungkyu Song; Taehui Na; Jisu Kim; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit. - Younghwi Yang; Juhyun Park; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Energy-Efficient All-Digital Time-Domain-Based CMOS Temperature Sensor for SoC Thermal Management. - Young-Jae An; Dong-Hoon Jung; Kyungho Ryu; Seung-Han Woo; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Trip-Point Bit-Line Precharge Sensing Scheme for Single-Ended SRAM. - Hanwool Jeong; Taewon Kim; Taejoong Song; Gyu-Hong Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Architecture-Aware Analytical Yield Model for Read Access in Static Random Access Memory. - Heechai Kang; Jisu Kim; Hanwool Jeong; Younghwi Yang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Level-Converting Retention Flip-Flop for Reducing Standby Power in ZigBee SoCs. - Jung-Hyun Park; Heechai Kang; Dong-Hoon Jung; Kyungho Ryu; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. - Younghwi Yang; Juhyun Park; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Area-optimal sensing circuit designs in deep submicrometer STT-RAM. - Sara Choi; Taehui Na; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISCAS, 2016)

WL under-driving scheme with decremental step voltage and incremental step time for high-capacity NAND flash memory. - Junyoung Ko; Younghwi Yang; Seong-Ook Jung; Jisu Kim; Cheon An Lee; Young-Sun Min; Jin-Young Chun; Moosung Kim (ISCAS, 2016)

Equalization scheme analysis for high-density spin transfer torque random access memory. - Beomsang Yoo; Taehui Na; Byungkyu Song; Seong-Ook Jung; Jung Pill Kim; Seung-Hyuk Kang (ISOCC, 2016)

Thermal and solar energy harvesting boost converter with time-multiplexing MPPT algorithm. - Dong-Hoon Jung; Ki-Ryong Kim; Seong-Ook Jung (IEICE Electron. Express, 2016)

Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM. - Hanwool Jeong; Juhyun Park; Tae Woo Oh; Woojin Rim; Taejoong Song; Gyu-Hong Kim; Hyo-Sig Won; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Transient Cell Supply Voltage Collapse Write Assist Using Charge Redistribution. - Ki-Ryong Kim; Hanwool Jeong; Juhyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Read Disturbance Reduction Technique for Offset-Canceling Dual-Stage Sensing Circuits in Deep Submicrometer STT-RAM. - Taehui Na; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. - Younghwi Yang; Hanwool Jeong; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator. - Young-Jae An; Dong-Hoon Jung; Kyungho Ryu; Hyuck-Sang Yim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM. - Sara Choi; Taehui Na; Jisu Kim; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation. - Kyoman Kang; Hanwool Jeong; Younghwi Yang; Juhyun Park; Ki-Ryong Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM. - Taehui Na; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM. - Taehui Na; Jisu Kim; Byungkyu Song; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator. - Kyungho Ryu; Jiwan Jung; Dong-Hoon Jung; Jin Hyuk Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2016)

GRO-TDC with gate-switch-based delay cell halving resolution limit. - Jung-Hyun Park; Dong-Hoon Jung; Seong-Ook Jung (Int. J. Circuit Theory Appl., 2017)

Offset-Canceling Current-Sampling Sense Amplifier for Resistive Nonvolatile Memory in 65 nm CMOS. - Taehui Na; Byungkyu Song; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE J. Solid State Circuits, 2017)

SRAM Operational Mismatch Corner Model for Efficient Circuit Design and Yield Analysis. - Tae Hoon Choi; Hanwool Jeong; Younghwi Yang; Juhyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Incremental Bitline Voltage Sensing Scheme With Half-Adaptive Threshold Reference Scheme in MLC PRAM. - Junyoung Ko; Younghwi Yang; Jisu Kim; Younghoon Oh; Hyun Kook Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Pre-Charged Local Bit-Line Sharing SRAM Architecture for Near-Threshold Operation. - Tae Woo Oh; Hanwool Jeong; Juhyun Park; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 10T-4MTJ Nonvolatile Ternary CAM Cell for Reliable Search Operation and a Compact Area. - Byungkyu Song; Taehui Na; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

Power-Gated 9T SRAM Cell for Low-Energy Operation. - Tae Woo Oh; Hanwool Jeong; Kyoman Kang; Juhyun Park; Younghwi Yang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Novel Heat-Aware Write Method with Optimized Heater Material and Structure in sub-20 nm PRAM for Low Energy Operation. - Hyun Kook Park; Tae Woo Oh; Seong-Ook Jung (ICECS, 2018)

Triplet-based Spike Timing Dependent Plasticity Circuit Design for three-terminal Spintronic Synapse. - Beomsang Yoo; Ki-Ryong Kim; Seong-Ook Jung (ICECS, 2018)

SRAM Cell with Data-Aware Power-Gating Write-Asist for Near-Threshold Operation. - Tae Woo Oh; Seong-Ook Jung (ISCAS, 2018)

Analysis on Sensing Yield of Voltage Latched Sense Amplifier for Low Power DRAM. - Suk Min Kim; Byungkyu Song; Tae Woo Oh; Seong-Ook Jung (PRIME, 2018)

0.293-mm2 Fast Transient Response Hysteretic Quasi-V2 DC-DC Converter With Area-Efficient Time-Domain-Based Controller in 0.35-µm CMOS. - Dong-Hoon Jung; Ki-Ryong Kim; Sunghwan Jo; Seong-Ook Jung (IEEE J. Solid State Circuits, 2018)

Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. - Taehui Na; Byungkyu Song; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation. - Hanwool Jeong; Tae Woo Oh; Seung Chul Song; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2018)

All-Digital Process-Variation-Calibrated Timing Generator for ATE With 1.95-ps Resolution and Maximum 1.2-GHz Test Rate. - Dong-Hoon Jung; Kyungho Ryu; Jung-Hyun Park; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{ mathrm{MIN}}$ Improvement and Energy Saving. - Hanwool Jeong; Se Hyeok Oh; Tae Woo Oh; Hoonki Kim; Changnam Park; Woojin Rim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time. - Hanwool Jeong; Juhyun Park; Seung Chul Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)

Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region. - Byungkyu Song; Sara Choi; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories. - Sara Choi; Hong Keun Ahn; Byungkyu Song; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Sensing Margin Enhancement Technique Utilizing Boosted Reference Voltage for Low-Voltage and High-Density DRAM. - Suk Min Kim; Byungkyu Song; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Variation-Tolerant WL Driving Scheme for High-Capacity NAND Flash Memory. - Junyoung Ko; Younghwi Yang; Jisu Kim; Cheon An Lee; Young-Sun Min; Jin-Young Chun; Moosung Kim; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS. - Taehui Na; Byungkyu Song; Sara Choi; Jung Pill Kim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2019)

A Read Voltage Modulation Technique for Leakage Current Compensation in Cross-Point OTS-PRAM. - Kwang Woo Lee; Hyun Kook Park; Seong-Ook Jung (ISCAS, 2020)

An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache. - Tae Hyun Kim; Hanwool Jeong; Juhyun Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Access, 2020)

Area- and Energy-Efficient STDP Learning Algorithm for Spiking Neural Network SoC. - Giseok Kim; Ki-Ryong Kim; Sara Choi; Hyo Jung Jang; Seong-Ook Jung (IEEE Access, 2020)

CNN Acceleration With Hardware-Efficient Dataflow for Super-Resolution. - Sumin Lee; Sunghwan Jo; Hong Keun Ahn; Seong-Ook Jung (IEEE Access, 2020)

Current Measurement Transducer Based on Current-To-Voltage-To-Frequency Converting Ring Oscillator with Cascade Bias Circuit. - Jongha Park; Jung-Hyun Park; Seong-Ook Jung (Sensors, 2020)

One-Sided Schmitt-Trigger-Based 9T SRAM Cell for Near-Threshold Operation. - Keonhee Cho; Juhyun Park; Tae Woo Oh; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020)

Highly Independent MTJ-Based PUF System Using Diode-Connected Transistor and Two-Step Postprocessing for Improved Response Stability. - Sehee Lim; Byungkyu Song; Seong-Ook Jung (IEEE Trans. Inf. Forensics Secur., 2020)

A Novel Matchline Scheduling Method for Low-Power and Reliable Search Operation in Cross-Point-Array Nonvolatile Ternary CAM. - Hyun Kook Park; Hong Keun Ahn; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2020)

pMOS Pass Gate Local Bitline SRAM Architecture With Virtual $V_{ mathrm{SS}}$ for Near-Threshold Operation. - Juhyun Park; Tae Woo Oh; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2020)

High Performance and Area Efficient Ferroelectric FET based Reconfigurable Logic Circuit. - Dong Han Ko; Sehee Lim; Young Kyu Lee; Seong-Ook Jung (ISOCC, 2021)

CNN encryption using XOR Gate for Hardware Optimization. - Ki Beom Lee; Sumin Lee; Sunghwan Joo; Hong Keun Ahn; Young Seok Jung; Seong-Ook Jung (ISOCC, 2021)

Intrinsic Capacitance based Multi bit Computing in Memory. - Young Kyu Lee; Minjune Yeo; Seokhee Cho; Seong-Ook Jung (ISOCC, 2021)

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased with Technology Scaling. - Keonhee Cho; Heekyung Choi; In Jun Jung; Ji Sang Oh; Tae Woo Oh; Ki-Ryong Kim; Giseok Kim; Taemin Choi; Changsoo Sim; Taejoong Song; Seong-Ook Jung (VLSI Circuits, 2021)

All-Bit-Line Read Scheme With Locking Bit-Line and Amplifying Sense Node in NAND Flash. - Jun Ho An; Jin Young Chun; Hyun Kook Park; Seong-Ook Jung (IEEE Access, 2021)

Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM. - Ki-Ryong Kim; Tae Woo Oh; Seong-Ook Jung (IEEE Access, 2021)

High-Performance and Area-Efficient Ferroelectric FET-Based Nonvolatile Flip-Flops. - Se Keon Kim; Tae Woo Oh; Sehee Lim; Dong Han Ko; Seong-Ook Jung (IEEE Access, 2021)

Comparative Analysis and Energy-Efficient Write Scheme of Ferroelectric FET-Based Memory Cells. - Dong Han Ko; Tae Woo Oh; Sehee Lim; Se Keon Kim; Seong-Ook Jung (IEEE Access, 2021)

Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation. - Ji Sang Oh; Juhyun Park; Keonhee Cho; Tae Woo Oh; Seong-Ook Jung (IEEE Access, 2021)

A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation. - Hanwool Jeong; Tae Hyun Kim; Changnam Park; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2021)

Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction. - Sara Choi; Hong Keun Ahn; Byungkyu Song; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Imbalance-Tolerant Bit-Line Sense Amplifier for Dummy-Less Open Bit-Line Scheme in DRAM. - Suk Min Kim; Byungkyu Song; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 6.9-μm2 3.26-ns 31.25-fj Robust Level Shifter With Wide Voltage and Frequency Ranges. - Ki-Ryong Kim; Ji Young Kim; Byoung-Mo Moon; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 0.166 pJ/b/pF, 3.5-5 Gb/s TSV I/O Interface With VOH Drift Control. - Ji-Young Kim; Jongsoo Lee; Ki-Ryong Kim; Byoung-Mo Moon; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

STT-MRAM Sensing: A Review. - Taehui Na; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Environmental-Variation-Tolerant Magnetic Tunnel Junction-Based Physical Unclonable Function Cell With Auto Write-Back Technique. - Byungkyu Song; Sehee Lim; Seung-Hyuk Kang; Seong-Ook Jung (IEEE Trans. Inf. Forensics Secur., 2021)

Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM. - Kwang Woo Lee; Hyun Kook Park; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2021)

SIF-NPU: A 28nm 3.48 TOPS/W 0.25 TOPS/mm2 CNN Accelerator with Spatially Independent Fusion for Real-Time UHD Super-Resolution. - Sumin Lee; Ki-Beom Lee; Sunghwan Joo; Hong Keun Ahn; Junghyup Lee; Dohyung Kim 006; Bumsub Ham; Seong-Ook Jung (ESSCIRC, 2022)

A Highly Integrated Crosspoint Array Using Self-rectifying FTJ for Dual-mode Operations: CAM and PUF. - Sehee Lim; Youngin Goh; Young Kyu Lee; Dong Han Ko; Junghyeon Hwang; Minki Kim; Yeongseok Jeong; Hunbeom Shin; Sanghun Jeon; Seong-Ook Jung (ESSCIRC, 2022)

A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications. - Keonhee Cho; Giseok Kim; Ji Sang Oh; Ki-Ryong Kim; Changsu Sim; Younmee Bae; Mijung Kim; Sangyeop Baeck; Taejoong Song; Seong-Ook Jung (VLSI Technology and Circuits, 2022)

A Low Power TSV I/O with Data Rate up to 10 Gb/s for Next Generation HBM. - Ji-Young Kim; Taeryeong Kim; Jeonghyeok You; Ki-Ryong Kim; Byoung-Mo Moon; Kyomin Sohn; Seong-Ook Jung (VLSI Technology and Circuits, 2022)

SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling. - Keonhee Cho; Heekyung Choi; In Jun Jung; Ji Sang Oh; Tae Woo Oh; Ki-Ryong Kim; Giseok Kim; Taemin Choi; Changsu Sim; Taejoong Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2022)

A 5 Gb/s Time-Interleaved Voltage-Mode Duobinary Encoding Scheme for 3-D-Stacked IC. - Ji-Young Kim; Jongsoo Lee; Ki-Ryong Kim; Sunghwan Jo; Byoung-Mo Moon; Kyomin Sohn; Seong-Ook Jung (IEEE J. Solid State Circuits, 2022)

A Sneak Current Compensation Scheme With Offset Cancellation Sensing Circuit for ReRAM-Based Cross-Point Memory Array. - Tae-Hyun Kim; Byungkyu Song; In Jun Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

SRAM Write Assist Circuit Using Cell Supply Voltage Self-Collapse With Bitline Charge Sharing for Near-Threshold Operation. - Keonhee Cho; Juhyun Park; Ki-Ryong Kim; Tae Woo Oh; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Static Contention-Free Dual-Edge-Triggered Flip-Flop with Redundant Internal Node Transition Elimination for Ultra-Low-Power Applications. - Sekeon Kim; Keonhee Cho; Kyeongrim Baek; Hyunjun Kim; Younmee Bae; Mijung Kim; Dongwook Seo; Sangyeop Baeck; Sungjae Lee; Seong-Ook Jung (VLSI Technology and Circuits, 2023)

A Low-Voltage Area-Efficient TSV I/O for HBM with Data Rate up to 15Gb/s Featuring Overlapped Multiplexing Driver, ISI Compensators and QEC. - Taeryeong Kim; Ji-Young Kim; Jeonghyeok You; Hohyun Chae; Byoung-Mo Moon; Kyomin Sohn; Seong-Ook Jung (VLSI Technology and Circuits, 2023)

Dual-Mode Operations of Self-Rectifying Ferroelectric Tunnel Junction Crosspoint Array for High-Density Integration of IoT Devices. - Sehee Lim; Youngin Goh; Young Kyu Lee; Dong Han Ko; Junghyeon Hwang; Yeongseok Jeong; Hunbeom Shin; Sanghun Jeon; Seong-Ook Jung (IEEE J. Solid State Circuits, 2023)

Local Bit-Line SRAM Architecture With Data-Aware Power-Gating Write Assist. - Tae Woo Oh; Juhyun Park; Tae Hyun Kim; Keonhee Cho; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Cross-Coupled Ferroelectric FET-Based Ternary Content Addressable Memory With Energy-Efficient Match Line Scheme. - Sehee Lim; Dong Han Ko; Se Keon Kim; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

High-Precision and Low-Power Offset Canceling Tri-State Sensing Latch in NAND Flash Memory. - Taeyun Lee; In Jun Jung; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Boosted Internal-Voltage-Difference. - In Jun Jung; Tae-Hyun Kim; Keonhee Cho; Ki-Ryong Kim; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Energy-Efficient Design of TSV I/O for HBM With a Data Rate up to 10 Gb/s. - Ji-Young Kim; Taeryeong Kim; Jeonghyeok You; Ki-Ryong Kim; Byoung-Mo Moon; Kyomin Sohn; Seong-Ook Jung (IEEE J. Solid State Circuits, 2023)

DPe-CIM: A 4T1C Dual-Port eDRAM Compute-in-Memory for Simultaneous Computing and Refresh with Adaptive Refresh and Data Conversion Reduction Scheme. - Dohan Kim 005; Minyoung Jo; Gi-Seok Kim; Dong-Gyun Ha; Ung-Bin Oh; Seong-Ook Jung (A-SSCC, 2024)

Post-Layout Parasitic Capacitance Prediction Methodology Using Bayesian Optimization. - Giseok Kim; Jaehyun Park 014; Seong-Ook Jung (ICEIC, 2024)

15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node. - Minjune Yeo; Keonhee Cho; Giseok Kim; Won Joon Jo; Jisang Oh; Sekeon Kim; Kyeongrim Baek; Sungho Park; Seungjae Yei; Seong-Ook Jung (ISSCC, 2024)

Design of Physically Unclonable Function Using Ferroelectric FET With Auto Write-Back Technique for Resource-Limited IoT Security. - Sehee Lim; Junghyeon Hwang; Dong Han Ko; Se Keon Kim; Tae Woo Oh; Sanghun Jeon; Seong-Ook Jung (IEEE Internet Things J., 2024)

Ferroelectric FET Nonvolatile Sense-Amplifier-Based Flip-Flops for Low Voltage Operation. - Sekeon Kim; Sehee Lim; Dong Han Ko; Tae Woo Oh; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A CNN-Based Super-Resolution Processor With Short-Term Caching for Real-Time UHD Upscaling. - Hong Keun Ahn; Sumin Lee; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Charge-Domain 4T2C eDRAM Compute-in-Memory Macro With Enhanced Variation Tolerance and Low-Overhead Data Conversion Schemes. - In Jun Jung; Dohan Kim 005; Minyoung Jo; Dong Han Ko; Young Kyu Lee; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Split WL 6T SRAM-Based Bit Serial Computing-in-Memory Macro With High Signal Margin and High Throughput. - Young Kyu Lee; Dong Han Ko; Seokhee Cho; Minjune Yeo; Mingu Kang; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Contention-Free Wordline Supporting Circuit for High Wordline Resistance in Sub-10-nm SRAM Designs. - Tae-Hyun Kim; Juhyun Park; In Jun Jung; Hoonki Kim; Taejoong Song; Seong-Ook Jung (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Design and Analysis of Static-Free PAM-4 Transmitter for HBM TSV Interface. - Jeonghyeok You; Hohyun Chae; Taeryeong Kim; Ji Hoon Lee; Seong-Ook Jung (ICEIC, 2025)

SRAM BL Predriven Write Operation With Row and Voltage Auto-Tracking Replica BL in Resistance-Dominated Technology Nodes. - Keonhee Cho; Minjune Yeo; Seungjae Yei; Giseok Kim; Sangyeop Baeck; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Low-Voltage Area-Efficient TSV I/O With QEC Realizing Data Rate up to 15 Gb/s for TSV Interface. - Taeryeong Kim; Ji-Young Kim; Jeonghyeok You; Hohyun Chae; Byoung-Mo Moon; Kyomin Sohn; Seong-Ook Jung (IEEE J. Solid State Circuits, 2025)

Dual-Input Stacked Inverter-Based Single-Ended DRAM Sense Amplifier Using BL Switches for Low-Power High-Speed Sensing. - Sehee Lim; In Jun Jung; Gi Seok Kim; Dong Han Ko; Sumin Lee; Seong-Ook Jung (IEEE J. Solid State Circuits, 2025)