A 12 bit 250 MS/s 28 mW +70 dB SFDR DAC in 0.11 μm CMOS using controllable RZ window for wireless SoC integration. - Seonggeon Kim; Jaehyun Kang; Minjae Lee 001 (A-SSCC, 2014)

A 12 bit 250 MS/s 28 mW +70 dB SFDR non-50% RZ DAC in 0.11 µm CMOS using controllable RZ window for wireless SoC integration. - Seonggeon Kim; Jaehyun Kang; Minjae Lee 001 (Microelectron. J., 2016)

Modeling Random Clock Jitter Effect of High-Speed Current-Steering NRZ and RZ DAC. - Seonggeon Kim; Kang-Yoon Lee; Minjae Lee 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)