Energy efficient radio frequency communication systems for wireless microsensors. - SeongHwan Cho (2002)

A behavioral modeling approach to the design of a low jitter clock source. - Gabriele Manganaro; Sung-Ung Kwak; SeongHwan Cho; Anurag Pulincherry (IEEE Trans. Circuits Syst. II Express Briefs, 2003)

A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications. - SeongHwan Cho; Anantha P. Chadrakasan (IEEE J. Solid State Circuits, 2004)

Variable bandwidth allocation scheme for energy efficient wireless sensor network. - SeongHwan Cho; Kee-Eung Kim (ICC, 2005)

A low power pipelined analog-to-digital converter using series sampling capacitors. - SeongHwan Cho; Sungmin Ock; Sang-Hoon Lee; Joonsuk Lee (ISCAS (6), 2005)

A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator. - Jaewook Kim; SeongHwan Cho (ISCAS, 2006)

A power-optimized CMOS LC VCO with wide tuning range in 0.5-V supply. - Dongmin Park; SeongHwan Cho (ISCAS, 2006)

A Low Power Transmitter for Phase-Shift Keying Modulation Schemes. - Jaewon Lee; SeongHwan Cho (PIMRC, 2006)

A Quadrature Modulation Transmitter Using Two Frequency Synthesizers. - Jaewon Lee; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

An ultra low power UHF RFID tag front-end for EPCglobal Gen2 with novel clock-free decoder. - Sung-Jin Kim; Min-Chang Cho; Joonhyun Park; Kisuk Song; Yul Kim; SeongHwan Cho (ISCAS, 2008)

A Time-Based Bandpass ADC Using Time-Interleaved Voltage-Controlled Oscillators. - Young-Gyu Yoon; Jaewook Kim; Tae-Kwang Jang; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

A Bio-impedance Measurement System for Portable Monitoring of Heart Rate and Pulse Wave Velocity using Small Body Area. - Min-Chang Cho; Jee-Yeon Kim; SeongHwan Cho (ISCAS, 2009)

A 95nW Ring Oscillator-based Temperature Sensor for RFID Tags in 0.13µm CMOS. - Sunghyun Park; Changwook Min; SeongHwan Cho (ISCAS, 2009)

A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-µm CMOS. - Joonhee Lee; Sungjun Kim; Sehyung Jeon; Woojae Lee; SeongHwan Cho (IEICE Trans. Electron., 2009)

Introduction to the Special Section on the 2008 Asian Solid-State Circuits Conference (A-SSCC'08). - Hoi-Jun Yoo; SeongHwan Cho (IEEE J. Solid State Circuits, 2009)

CMRR enhancement technique for IA using three IAs for bio-medical sensor applications. - Woojae Lee; Min-Chang Cho; SeongHwan Cho (APCCAS, 2010)

A 10-bit 300MSample/s pipelined ADC using time-interleaved SAR ADC for front-end stages. - Young-Hwa Kim; Jaewon Lee; SeongHwan Cho (ISCAS, 2010)

A 2.4-GHz reference doubled fractional-N PLL with dual phase detector in 0.13-μm CMOS. - Woojae Lee; SeongHwan Cho (ISCAS, 2010)

A background KDCO compensation technique for constant bandwidth in all-digital phase-locked loop. - Sung-Pah Lee; SeongHwan Cho (ISCAS, 2010)

An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder. - Sung-Jin Kim; Min-Chang Cho; SeongHwan Cho (IEICE Trans. Electron., 2010)

Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter. - Jaewook Kim; Tae-Kwang Jang; Young-Gyu Yoon; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A time-domain flash ADC immune to voltage controlled delay line non-linearity. - Young-Hwa Kim; SeongHwan Cho (ASICON, 2011)

A fractional-N frequency synthesizer using high-OSR delta-sigma modulator and nested-PLL. - Pyoungwon Park; Dongmin Park; SeongHwan Cho (CICC, 2011)

A digital-intensive receiver front-end using VCO-based ADC with an embedded 2nd-Order anti-aliasing Sinc filter in 90nm CMOS. - Jaewook Kim; Wonsik Yu; Hyun-Kyu Yu; SeongHwan Cho (ISSCC, 2011)

A 470-µW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider With an In-Phase Dual-Input Injection Scheme. - Joonhee Lee; Sunghyun Park; SeongHwan Cho (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Session 19 overview: 20+ Gb/s wireline transceivers and injection-locked clocking: Wireline subcommittee. - Ken Chang; SeongHwan Cho (ISSCC, 2012)

Optical PCB interconnects, Niche or mainstream? - Ichiro Fujimori; SeongHwan Cho; Joshua Friedrich; John T. Stonick (ISSCC, 2012)

A 14.2mW 2.55-to-3GHz cascaded PLL with reference injection, 800MHz delta-sigma modulator and 255fsrms integrated jitter in 0.13μm CMOS. - Dongmin Park; SeongHwan Cho (ISSCC, 2012)

An all-digital clock generator using a fractionally injection-locked oscillator in 65nm CMOS. - Pyoungwon Park; Jaejin Park; Hojin Park; SeongHwan Cho (ISSCC, 2012)

A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. - KwangSeok Kim; Young-Hwa Kim; Wonsik Yu; SeongHwan Cho (VLSIC, 2012)

A High-Frequency Compensated Crosstalk and ISI Equalizer for Multi-Channel On-Chip Interconnect in 130-nm CMOS. - Jaewon Lee; Woojae Lee; SeongHwan Cho (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS. - Junghyup Lee; SeongHwan Cho (IEEE J. Solid State Circuits, 2012)

A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 μ m CMOS. - Dongmin Park; SeongHwan Cho (IEEE J. Solid State Circuits, 2012)

A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL. - Pyoungwon Park; Dongmin Park; SeongHwan Cho (IEEE J. Solid State Circuits, 2012)

A 2.5-Gb/s On-Chip Interconnect Transceiver With Crosstalk and ISI Equalizer in 130 nm CMOS. - Jaewon Lee; Woojae Lee; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A Highly-Digital VCO-Based Analog-to-Digital Converter Using Phase Interpolator and Digital Calibration. - Tae-Kwang Jang; Jaewook Kim; Young-Gyu Yoon; SeongHwan Cho (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A 148fsrms integrated noise 4MHz bandwidth all-digital second-order ΔΣ time-to-digital converter using gated switched-ring oscillator. - Wonsik Yu; KwangSeok Kim; SeongHwan Cho (CICC, 2013)

F5: Frequency generation and clock distribution. - Antonio Liscidini; SeongHwan Cho; Tony Chan Carusone; Tanay Karnik; Mike Keaveney; Brian Otis; Aaron Partridge; Christoph Sandner (ISSCC, 2013)

A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier. - KwangSeok Kim; Young-Hwa Kim; Wonsik Yu; SeongHwan Cho (IEEE J. Solid State Circuits, 2013)

A Time-Domain High-Order MASH ΔΣ ADC Using Voltage-Controlled Gated-Ring Oscillator. - Wonsik Yu; Jaewook Kim; KwangSeok Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A 9 bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. - KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE J. Solid State Circuits, 2014)

A 148fsrms Integrated Noise 4 MHz Bandwidth Second-Order ΔΣ Time-to-Digital Converter With Gated Switched-Ring Oscillator. - Wonsik Yu; KwangSeok Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS. - Hyojun Kim; Jinwoo Sang; Hyunik Kim; Youngwoo Jo; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2015)

5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs. - Junghyup Lee; Pyoungwon Park; SeongHwan Cho; Minkyu Je (ISSCC, 2015)

Integrated All Electrical Pulse Wave Velocity and Respiration Sensors Using Bio-Impedance. - Woojae Lee; SeongHwan Cho (IEEE J. Solid State Circuits, 2015)

A 0.22 ps rms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter. - Wonsik Yu; KwangSeok Kim; SeongHwan Cho (IEEE J. Solid State Circuits, 2015)

A Hybrid-Domain Two-Step Time-to-Digital Converter Using a Switch-Based Time-to-Voltage Converter and SAR ADC. - Jungho Kim; Young-Hwa Kim; KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS. - Hyunik Kim; Yongjo Kim; Taeik Kim; Hojin Park; SeongHwan Cho (ISSCC, 2016)

ES1: Student research preview. - Jan Van der Spiegel; SeongHwan Cho; Denis Daly (ISSCC, 2016)

New Associate Editors. - Michael P. Flynn; Pietro Andreani; SeongHwan Cho (IEEE J. Solid State Circuits, 2016)

A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source. - Young-Hwa Kim; SeongHwan Cho (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A 255nW ultra-high input impedance analog front-end for non-contact ECG monitoring. - JinSeok Lee; Hyojun Kim; SeongHwan Cho (CICC, 2017)

EE1: Student Research Preview. - SeongHwan Cho; Denis Daly (ISSCC, 2017)

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique. - Hyunik Kim; Yongjo Kim; Taeik Kim; Hyung Jong Ko; SeongHwan Cho (IEEE J. Solid State Circuits, 2017)

A 2.3-mW 0.01-mm2 1.25-GHz Quadrature Signal Corrector With 1.1-ps Error for Mobile DRAM Interface in 65-nm CMOS. - Yongjo Kim; Keunsoo Song; Dongkyun Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A supply noise insensitive PLL with a rail-to-rail swing ring oscillator and a wideband noise suppression loop. - Dongin Kim; SeongHwan Cho (ASP-DAC, 2018)

A 43.4μW photoplethysmogram-based heart-rate sensor using heart-beat-locked loop. - Do-Hun Jang; SeongHwan Cho (ISSCC, 2018)

A 2.69UW Dual Quantization-Based Capacitance-to-Digital Converter for Pressure, Humidity, and Acceleration Sensing in 0.18UM CMOS. - Sujin Park; Geon-Hwi Lee; SeongHwan Cho (VLSI Circuits, 2018)

An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback. - JinSeok Lee; Geon-Hwi Lee; Hyojun Kim; SeongHwan Cho (IEEE J. Solid State Circuits, 2018)

A Low-Power Photoplethysmogram-Based Heart Rate Sensor Using Heartbeat Locked Loop. - JinSeok Lee; Do-Hun Jang; Sujin Park; SeongHwan Cho (IEEE Trans. Biomed. Circuits Syst., 2018)

A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation. - Youngwoo Jo; Hyojun Kim; SeongHwan Cho (IEEE Trans. Very Large Scale Integr. Syst., 2018)

An On-Off Keying LC Oscillator-Based Acoustic Transmitter with Fast Turn-On and Turn-Off Time. - Eunseok Lee 002; Sujin Park; SeongHwan Cho (APCCAS, 2019)

A Low-Power Piezoelectric Speaker Driver Using LC Oscillator for Acoustic Communication. - Eunseok Lee 002; Sujin Park; Nahmil Koo; SeongHwan Cho (ISOCC, 2019)

A 27.8μW Biopotential Amplifier Tolerant to 30Vpp Common-Mode Interference for Two-Electrode ECG Recording in 0.18μm CMOS. - Nahmil Koo; SeongHwan Cho (ISSCC, 2019)

A 2.92-µW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-µm CMOS. - Sujin Park; Geon-Hwi Lee; SeongHwan Cho (IEEE J. Solid State Circuits, 2019)

An On-Chip Thermal Monitoring System With a Temperature Sensing Area of 52 µm2 in 180-nm CMOS. - Dong-Kyun Jung; Jin-O. Seo; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise. - Dongin Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits. - Dongin Kim; KwangSeok Kim; Wonsik Yu; SeongHwan Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Capacitance-to-Digital Converter with Differential Bondwire Accelerometer, On-chip Air Pressure and Humidity Sensor in 0.18 μm CMOS. - Sujin Park; Geon-Hwi Lee; Seungmin Oh; SeongHwan Cho (ASP-DAC, 2020)

An Adaptive Clocking System using Supply Tracking Clock Modulator with Background Calibrated Supply-Sensitivity in 28nm CMOS. - Dongin Kim; SeongHwan Cho (A-SSCC, 2021)

An Offset Charge Compensating Biphasic Neuro - stimulation for Faradaic DC-Current Reduction. - Donghyeok Cho; Nahmil Koo; Taekwang Jang; SeongHwan Cho (ISCAS, 2021)

28.6 A 22.6µ W Biopotential Amplifier with Adaptive Common-Mode Interference Cancelation Achieving Total-CMRR of 104dB and CMI Tolerance of 15Vpp in 0.18µm CMOS. - Nahmil Koo; Hyojun Kim; SeongHwan Cho (ISSCC, 2021)

An Energy-Efficient Voltage Step-up System for 3D NAND Flash using Charge-Compensating Regulator. - Hyunsik Jeong; SeongHwan Cho (VLSI Circuits, 2021)

A 3.68aFrms Resolution 183dB FoMs 4th-order Continuous-Time Bandpass ∆Σ Capacitance-to-Digital Converter in 0.18µm CMOS. - Sujin Park; Hyungil Chae; SeongHwan Cho (VLSI Circuits, 2021)

A Single BJT Bandgap Reference With Frequency Compensation Exploiting Mirror Pole. - Myungjun Kim; SeongHwan Cho (IEEE J. Solid State Circuits, 2021)

A 24.8-μW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180-nm CMOS. - Nahmil Koo; SeongHwan Cho (IEEE J. Solid State Circuits, 2021)

Reduction of Motion Artifact in PPG signal with CDS-LMS Filter. - Woobean Lee; Pangi Park; SeongHwan Cho (APCCAS, 2022)

A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter. - Yeonwook Jung; Seongseop Lee; Hyojun Kim; SeongHwan Cho (ISSCC, 2022)

ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory. - Jin-O. Seo; Mingoo Seok; SeongHwan Cho (ISSCC, 2022)

A 2.54μJ∙ppm2-FOMS Supply- and Temperature-Independent Time-Locked ΔΣ Capacitance-to-Digital Converter in 0.18-μm CMOS. - Seungyeob Baik; Taeryoung Seol; Sehwan Lee; Geunha Kim; SeongHwan Cho; Arup K. George; Junghyup Lee (VLSI Technology and Circuits, 2022)

A Comprehensive Analysis of Today's Malware and Its Distribution Network: Common Adversary Strategies and Implications. - Siwon Huh; SeongHwan Cho; Jinho Choi; Seungwon Shin 001; Hojoon Lee 001 (IEEE Access, 2022)

Technique for fast triangular chirp modulation in FMCW PLL. - Han-Gil Choi; Sang Heung Lee; SeongHwan Cho (IEICE Electron. Express, 2022)

A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance. - Sujin Park; Ji-Hwan Seol; Li Xu 006; SeongHwan Cho; Dennis Sylvester; David T. Blaauw (IEEE J. Solid State Circuits, 2022)

A Jitter-Programmable Bang-Bang Phase-Locked Loop Using PVT Invariant Stochastic Jitter Monitor. - Yongjo Kim; Taekwang Jang; SeongHwan Cho (A-SSCC, 2023)

A 1, 024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing. - Woojun Choi; Yiyang Chen; Donghwan Kim; Sean Weaver; Tilman Schlotter; Can Livanelioglu; Jiawei Liao; Rosario M. Incandela; Parham Davami; Gabriele Atzeni; Sina Arjmandpour; SeongHwan Cho; et al. (VLSI Technology and Circuits, 2023)

A Supply-Noise-Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM. - Yeonwook Jung; Seongseop Lee; Hyojun Kim; SeongHwan Cho (IEEE J. Solid State Circuits, 2023)

A 3.68 aFrms Resolution Continuous-Time Bandpass Δ Σ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS. - Sujin Park; Hyungil Chae; SeongHwan Cho (IEEE J. Solid State Circuits, 2023)

A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 Vpp and T-CMRR of 105 dB in 180-nm CMOS. - Nahmil Koo; Hyojun Kim; SeongHwan Cho (IEEE J. Solid State Circuits, 2023)

An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier. - Myungjun Kim; SeongHwan Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Introduction to the Special Section on the 2022 Asian Solid-State Circuits Conference (A-SSCC). - SeongHwan Cho; Joo-Young Kim 001; Minoru Fujishima; Jun Zhou 017 (IEEE J. Solid State Circuits, 2023)

An Adaptive Filter Based Motion Artifact Cancellation Technique Using Multi-Wavelength PPG for Accurate HR Estimation. - Pangi Park; Woobean Lee; SeongHwan Cho (IEEE Trans. Biomed. Circuits Syst., 2023)

A Stochastic RMS Jitter Monitoring Circuit for Clock Generators using Central Limit Theorem. - Hyeonmin Park; Ahryung Kim; Jeyeon Lee; SeongHwan Cho (APCCAS, 2024)

A Fully Integrated 4: 1 DC-DC Converter Using Electromagnetically Coupled Class-D LC Oscillators Achieving 74.5% Peak Efficiency and 0.78W/mm² Peak Power Density. - Donghyeok Cho; Taekwang Jang; SeongHwan Cho (A-SSCC, 2024)

19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur. - Hangil Choi; SeongHwan Cho (ISSCC, 2024)

3.1 A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4ppm/°C from -20°C to 125°C. - Pangi Park; Junghyup Lee; SeongHwan Cho (ISSCC, 2024)

A 44.2-TOPS/W CNN Processor With Variation-Tolerant Analog Datapath and Variation Compensating Circuit. - Jin-O. Seo; Mingoo Seok; SeongHwan Cho (IEEE J. Solid State Circuits, 2024)

A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor. - Yongjo Kim; Taekwang Jang; SeongHwan Cho (IEEE J. Solid State Circuits, 2024)

A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120× Multiplying Factor and 92.3-fs RMS Jitter Including Reference Spur. - Hangil Choi; SeongHwan Cho (IEEE J. Solid State Circuits, 2024)

A PVT-Insensitive Sub-Ranging Current Reference Achieving 11.4-ppm/ ° C From -20 °C to 125 °C. - Pangi Park; Junghyup Lee; SeongHwan Cho (IEEE J. Solid State Circuits, 2024)

37.8 A 13.5µW 35-Keyword End-to-End Keyword Spotting System Featuring Personalized On-Chip Training in 28nm CMOS. - Hyuk-Jin Lee; Kyunghoon Pyo; Taekwang Jang; Mingoo Seok; SeongHwan Cho (ISSCC, 2025)

19.6 A 60GHz I/Q-Calibrated SSB-Mixer-Based LO with Sub-ns Settling Time and -56dBc Worst-Case Spur Using ILO Filter in 28nm CMOS. - Jaewon Oh; Cheol So; Hyojun Kim; Songcheol Hong; SeongHwan Cho (ISSCC, 2025)