Reducing memory access latency with asymmetric DRAM bank organizations. - Young Hoon Son; Seongil O; Yuhwan Ro; Jae W. Lee; Jung Ho Ahn (ISCA, 2013)

McSimA+: A manycore simulator with application-level+ simulation and detailed microarchitecture modeling. - Jung Ho Ahn; Sheng Li 007; Seongil O; Norman P. Jouppi (ISPASS, 2013)

Row-buffer decoupling: A case for low-latency DRAM microarchitecture. - Seongil O; Young Hoon Son; Nam Sung Kim; Jung Ho Ahn (ISCA, 2014)

Microbank: Architecting Through-Silicon Interposer-Based Main Memory Systems. - Young Hoon Son; Seongil O; Hyunggyun Yang; Daejin Jung; Jung Ho Ahn; John Kim 001; Jangwoo Kim; Jae W. Lee (SC, 2014)

CiDRA: A cache-inspired DRAM resilience architecture. - Young Hoon Son; Sukhan Lee 002; Seongil O; Sanghyuk Kwon; Nam Sung Kim; Jung Ho Ahn (HPCA, 2015)

History-Assisted Adaptive-Granularity Caches (HAAG$) for High Performance 3D DRAM Architectures. - Ke Chen 020; Sheng Li 007; Jung Ho Ahn; Naveen Muralimanohar; Jishen Zhao; Cong Xu 002; Seongil O; Yuan Xie 001; Jay B. Brockman; Norman P. Jouppi (ICS, 2015)

Architecting to achieve a billion requests per second throughput on a single key-value store server platform. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (ISCA, 2015)

CIDR: A Cache Inspired Area-Efficient DRAM Resilience Architecture against Permanent Faults. - Seongil O; Sanghyuk Kwon; Young Hoon Son; Yujin Park; Jung Ho Ahn (IEEE Comput. Archit. Lett., 2015)

Achieving One Billion Key-Value Requests per Second on a Single Server. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (IEEE Micro, 2016)

Full-Stack Architecting to Achieve a Billion-Requests-Per-Second Throughput on a Single Key-Value Store Server Platform. - Sheng Li 007; Hyeontaek Lim; Victor W. Lee; Jung Ho Ahn; Anuj Kalia; Michael Kaminsky; David G. Andersen; Seongil O; Sukhan Lee 002; Pradeep Dubey (ACM Trans. Comput. Syst., 2016)

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. - Sang-uhn Cha; Seongil O; Hyunsung Shin; Sangjoon Hwang; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Gyo-Young Jin; Young Hoon Son; Hyunyoon Cho; Jung Ho Ahn; Nam Sung Kim (HPCA, 2017)

3D-Xpath: high-density managed DRAM architecture with cost-effective alternative paths for memory transactions. - Sukhan Lee 002; Kiwon Lee; Min Chul Sung; Mohammad Alian; Chankyung Kim; Wooyeong Cho; Reum Oh; Seongil O; Jung Ho Ahn; Nam Sung Kim (PACT, 2018)

Hardware Architecture and Software Stack for PIM Based on Commercial DRAM Technology : Industrial Product. - Sukhan Lee 002; Shinhaeng Kang; Jaehoon Lee 005; Hyeonsu Kim; Eojin Lee; Seungwoo Seo; Hosang Yoon; Seungwon Lee; Kyounghwan Lim; Hyunsung Shin; Jinhyun Kim; Seongil O; et al. (ISCA, 2021)

25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications. - Young-Cheon Kwon; Sukhan Lee 002; Jaehoon Lee 005; Sang-Hyuk Kwon; Je-Min Ryu; Jong-Pil Son; Seongil O; Hak-soo Yu; Haesuk Lee; Soo Young Kim; Youngmin Cho; Jin Guk Kim; et al. (ISSCC, 2021)

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. - Dae-Hyun Kim 003; Byungkyu Song; Hyun-A. Ahn; Woongjoon Ko; Sung-Geun Do; Seokjin Cho; Kihan Kim; Seung-Hoon Oh; Hye-Yoon Joo; Geuntae Park; Jin-Hun Jang; Yong-Hun Kim; et al. (ISSCC, 2022)