Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. - Seongjae Cho; Jang-Gn Yun; Il-Han Park; Jung Hoon Lee; Jong Pil Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2007)

Design and Simulation of Asymmetric MOSFETs. - Jong Pil Kim; Woo Young Choi; Jae Young Song; Seongjae Cho; Sang Wan Kim; Jong Duk Lee; Byung-Gook Park (IEICE Trans. Electron., 2007)

Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs. - Hochul Lee; Youngchang Yoon; Seongjae Cho; Hyungcheol Shin (IEICE Trans. Electron., 2007)

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). - Seongjae Cho; Il-Han Park; Jung Hoon Lee; Jang-Gn Yun; Doo-Hyun Kim; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2008)

Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. - Jang-Gn Yun; Il-Han Park; Seongjae Cho; Jung Hoon Lee; Doo-Hyun Kim; Gil Sung Lee; Yoon Kim; Jong Duk Lee; Byung-Gook Park (IEICE Trans. Electron., 2008)

Design Consideration for Vertical Nonvolatile Memory Device Regarding Gate-Induced Barrier Lowering (GIBL). - Seongjae Cho; Jung Hoon Lee; Gil Sung Lee; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array. - Yoon Kim; Seongjae Cho; Gil Sung Lee; Il-Han Park; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory. - Doo-Hyun Kim; Il-Han Park; Seongjae Cho; Jong Duk Lee; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2009)

Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation. - Sang Hyuk Park; Sangwoo Kang; Seongjae Cho; Dong-Seup Lee; Jung Han Lee; Hong-Seon Yang; Kwon-Chil Kang; Joung-Eob Lee; Jong Duk Lee; Byung-Gook Park (IEICE Trans. Electron., 2009)

Nanosculpture: Three-dimensional CMOS device structures for the ULSI era. - Byung-Gook Park; Jae Young Song; Jong Pil Kim; Hoon Jeong; Jung Hoon Lee; Seongjae Cho (Microelectron. J., 2009)

Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs. - Seongjae Cho; In Man Kang; Kyung Rok Kim (IEICE Electron. Express, 2010)

Simulation Study on Dependence of Channel Potential Self-Boosting on Device Scale and Doping Concentration in 2-D and 3-D NAND-Type Flash Memory Devices. - Seongjae Cho; Jung Hoon Lee; Yoon Kim; Jang-Gn Yun; Hyungcheol Shin; Byung-Gook Park (IEICE Trans. Electron., 2010)

Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer. - Dong-Seup Lee; Hong-Seon Yang; Kwon-Chil Kang; Joung-Eob Lee; Jung Han Lee; Seongjae Cho; Byung-Gook Park (IEICE Trans. Electron., 2010)

A New 1T DRAM Cell: Cone Type 1T DRAM Cell. - Gil Sung Lee; Doo-Hyun Kim; Seongjae Cho; Byung-Gook Park (IEICE Trans. Electron., 2011)

Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance. - Seongjae Cho; Hyungjin Kim 001; Min-Chul Sun; In Man Kang; Byung-Gook Park; James S. Harris Jr. (IEICE Electron. Express, 2012)

Vertical stack array of one-time programmable nonvolatile memory based on pn-junction diode and its operation scheme for faster access. - Seongjae Cho; Sunghun Jung; Sungjun Kim; Byung-Gook Park (IEICE Electron. Express, 2014)

InGaAs/Si Heterojunction Tunneling Field-Effect Transistor on Silicon Substrate. - Sung Yun Woo; Young Jun Yoon; Jae Hwa Seo; Gwan Min Yoo; Seongjae Cho; In Man Kang (IEICE Trans. Electron., 2014)

Ge-on-Si photodetector with novel metallization schemes for on-chip optical interconnect. - Mina Yun; Seongjae Cho; Sae-Kyoung Kang; Sunghun Jung; Byung-Gook Park (ISCE, 2015)

Resistive Switching Characteristics of Silicon Nitride-Based RRAM Depending on Top Electrode Metals. - Sungjun Kim; Sunghun Jung; Min-Hwi Kim; Seongjae Cho; Byung-Gook Park (IEICE Trans. Electron., 2015)

Bias Polarity Dependent Resistive Switching Behaviors in Silicon Nitride-Based Memory Cell. - Sungjun Kim; Min-Hwi Kim; Seongjae Cho; Byung-Gook Park (IEICE Trans. Electron., 2016)

Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory. - Jae Yoon Lee; Youngmin Kim; Ikhyeon Kworn; Il Hwan Cho; Jae Yeon Lee; Soo Gil Kim; Seongjae Cho (DRC, 2018)

Insertion of Ag Layer in TiN/SiNx/TiN RRAM and Its Effect on Filament Formation Modeled by Monte Carlo Simulation. - Yeon-Joon Choi; Min-Hwi Kim; Suhyun Bang; Tae-Hyeon Kim; Dong Keun Lee; Kyungho Hong; Chae Soo Kim; Sungjun Kim; Seongjae Cho; Byung-Gook Park (IEEE Access, 2020)

Zinc Tin Oxide Synaptic Device for Neuromorphic Engineering. - Ji-Ho Ryu; Boram Kim; Fayyaz Hussain; Muhammad Ismail; Chandreswar Mahata; Teresa Oh; Muhammad Imran; Kyung Kyu Min; Tae-Hyeon Kim; Byung-Do Yang; Seongjae Cho; Byung-Gook Park; et al. (IEEE Access, 2020)

Threshold-Variation-Tolerant Coupling-Gate α-IGZO Synaptic Transistor for More Reliably Controllable Hardware Neuromorphic System. - Dongyeon Kang; Jun Tae Jang; Shinyoung Park; Md. Hasan Raza Ansari; Jong-Ho Bae; Sung-Jin Choi; Dong Myong Kim; Changwook Kim; Seongjae Cho; Dae Hwan Kim (IEEE Access, 2021)

A Compact Integrate-and-Fire Neuron Circuit Embedding Operational Transconductance Amplifier for Fidelity Enhancement. - Arati Kumari Shah; Eou-Sik Cho; Jisun Park 002; Hyungsoon Shin; Seongjae Cho (IEEE Access, 2023)

An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network. - Arati Kumari Shah; Kannan Udaya Mohanan; Jisun Park 002; Hyungsoon Shin; Eou-Sik Cho; Seongjae Cho (IET Circuits Devices Syst., 2023)

Optimization of the structural complexity of artificial neural network for hardware-driven neuromorphic computing application. - Kannan Udaya Mohanan; Seongjae Cho; Byung-Gook Park (Appl. Intell., 2023)

Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET. - Soomin Kim; Seongjae Cho (ICEIC, 2024)