Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. - Seongmoo Heo; Kenneth C. Barr; Mark Hampton; Krste Asanovic (ISCA, 2002)

Reducing power density through activity migration. - Seongmoo Heo; Kenneth C. Barr; Krste Asanovic (ISLPED, 2003)

Power-optimal pipelining in deep submicron technology. - Seongmoo Heo; Krste Asanovic (ISLPED, 2004)

Replacing global wires with an on-chip network: a power analysis. - Seongmoo Heo; Krste Asanovic (ISLPED, 2005)

Optimal digital system design in deep submicron technology. - Seongmoo Heo (2006)

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. - Seongmoo Heo; Ronny Krashinsky; Krste Asanovic (IEEE Trans. Very Large Scale Integr. Syst., 2007)

8Gb 3D DDR3 DRAM using through-silicon-via technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Soon-Hong Ahn; Hoon Lee; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jin Ho Kim; Jae-Wook Lee 007; Han-Sung Joo; Woo-Seop Kim; et al. (ISSCC, 2009)

8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. - Uksong Kang; Hoeju Chung; Seongmoo Heo; Dukha Park; Hoon Lee; Jin Ho Kim; Soon-Hong Ahn; Sooho Cha; Jaesung Ahn; Dukmin Kwon; Jae-Wook Lee 007; Han-Sung Joo; et al. (IEEE J. Solid State Circuits, 2010)