Evaluator-executor transformation for efficient pipelining of loops with conditionals. - Yeonghun Jeong; Seongseok Seo; Jongeun Lee (ACM Trans. Archit. Code Optim., 2013)

Flattening-based mapping of imperfect loop nests for CGRAs? - Jongeun Lee; Seongseok Seo; Hongsik Lee; Hyeon Uk Sim (CODES+ISSS, 2014)

Configurable range memory for effective data reuse on programmable accelerators. - Jongeun Lee; Seongseok Seo; Jong Kyung Paek; Kiyoung Choi (ACM Trans. Design Autom. Electr. Syst., 2014)

Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures. - Hyeon Uk Sim; Hongsik Lee; Seongseok Seo; Jongeun Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)