LOG-CIM: A 116.4 TOPS/W Digital Computing-In-Memory Processor Supporting a Wide Range of Logarithmic Quantization with Zero-Aware 6T Dual-WL Cell. - Soyeon Um; Sangjin Kim; Seongyon Hong; Sangyeob Kim; Hoi-Jun Yoo (A-SSCC, 2023)

COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation. - Sangyeob Kim; Soyeon Kim; Seongyon Hong; Sangjin Kim; Donghyeon Han; Jiwon Choi; Hoi-Jun Yoo (COOL CHIPS, 2023)

A 332 TOPS/W Input/Weight-Parallel Computing-in-Memory Processor with Voltage-Capacitance-Ratio Cell and Time-Based ADC. - Seongyon Hong; Soyeon Um; Sangjin Kim; Sangyeob Kim; Wooyoung Jo; Hoi-Jun Yoo (ISCAS, 2023)

C-DNN: A 24.5-85.8TOPS/W Complementary-Deep-Neural-Network Processor with Heterogeneous CNN/SNN Core Architecture and Forward-Gradient-Based Sparsity Generation. - Sangyeob Kim; Soyeon Kim; Seongyon Hong; Sangjin Kim; Donghyeon Han; Hoi-Jun Yoo (ISSCC, 2023)

DualNet: Efficient Integration of Artificial Neural Network and Spiking Neural Network with Equivalent Conversion. - Seongyon Hong; Sangyeob Kim; Soyeon Kim; Hoi-Jun Yoo (AICAS, 2024)

A Low-Power Large-Language-Model Processor with Big-Little Network and Implicit-Weight-Generation for On-Device AI. - Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Soyeon Kim; Seongyon Hong; Nayeong Lee; Hoi-Jun Yoo (HCS, 2024)

A 28.6 mJ/iter Stable Diffusion Processor for Text-to-Image Generation with Patch Similarity-based Sparsity Augmentation and Text-based Mixed-Precision. - Jiwon Choi; Wooyoung Jo; Seongyon Hong; Beomseok Kwon; Wonhoon Park; Hoi-Jun Yoo (ISCAS, 2024)

20.5 C-Transformer: A 2.6-18.1μJ/Token Homogeneous DNN-Transformer/Spiking-Transformer Processor with Big-Little Network and Implicit Weight Generation for Large Language Models. - Sangyeob Kim; Sangjin Kim; Wooyoung Jo; Soyeon Kim; Seongyon Hong; Hoi-Jun Yoo (ISSCC, 2024)

Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow. - Seongyon Hong; Wooyoung Jo; Sangjin Kim; Sangyeob Kim; Kyomin Sohn; Hoi-Jun Yoo (VLSI Technology and Circuits, 2024)

COOL-NPU: Complementary Online Learning Neural Processing Unit. - Sangyeob Kim; Soyeon Kim; Seongyon Hong; Sangjin Kim; Jiwon Choi; Donghyeon Han; Hoi-Jun Yoo (IEEE Micro, 2024)

C-DNN: An Energy-Efficient Complementary Deep-Neural-Network Processor With Heterogeneous CNN/SNN Core Architecture. - Sangyeob Kim; Soyeon Kim; Seongyon Hong; Sangjin Kim; Donghyeon Han; Jiwon Choi; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

LOG-CIM: An Energy-Efficient Logarithmic Quantization Computing-In-Memory Processor With Exponential Parallel Data Mapping and Zero-Aware 6T Dual-WL Cell. - Soyeon Um; Sangjin Kim; Seongyon Hong; Sangyeob Kim; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2024)

A 65.1 TOPS/W Digital CIM Processor for Ultra-Low-Bit Transformers with Multiplexer-based Adder and Scaling Factor-based Reordering. - Nayeong Lee; Sangyeob Kim; Seongyon Hong; Jiwon Choi; Hoi-Jun Yoo (ISCAS, 2025)

A 17.1 TOPS/W FP-INT Transformer Inference Accelerator with Sparsity Boosting and Output Importance-Aware Processing. - Jeonggyu So; Seongyon Hong; Jiwon Choi; Wooyoung Jo; Sangjin Kim; Hoi-Jun Yoo; Donghyeon Han (ISCAS, 2025)

23.7 BROCA: A 52.4-to-559.2mW Mobile Social Agent System-on-Chip with Adaptive Bit-Truncate Unit and Acoustic-Cluster Bit Grouping. - Wooyoung Jo; Seongyon Hong; Jiwon Choi; Beomseok Kwon; Haoyang Sang; Dongseok Im; Sangyeob Kim; Sangjin Kim; Taekwon Lee; Hoi-Jun Yoo (ISSCC, 2025)

Dyamond: Compact and Efficient 1T1C DRAM IMC Accelerator With Bit Column Addition for Memory-Intensive AI. - Seongyon Hong; Wooyoung Jo; Sangjin Kim; Sangyeob Kim; Soyeon Um; Kyomin Sohn; Hoi-Jun Yoo (IEEE J. Solid State Circuits, 2025)