Memory Window Expansion for Ferroelectric FET based Multilevel NVM: Hybrid Solution with Combination of Polarization and Injected Charges. - Jae-Gil Lee; Joongsik Kim; Dong Ik Suh; Ildo Kim; Gwon Deok Han; Seung Wook Ryu; Seho Lee; Myung-Hee Na; Seonyong Cha; Hyeon Woo Park; Cheol Seong Hwang (IMW, 2022)

Recognition Accuracy Enhancement using Interface Control with Weight Variation-Lowering in Analog Computation-in-Memory. - Sangsu Park; Gyonhui Lee; Youngjae Kwon; Dong Ik Suh; Hanwool Lee; Sangeun Je; Dabin Kim; Dohan Lee; Seungwook Ryu; Seungbum Kim; Euiseok Kim; Sunghoon Lee; et al. (IMW, 2022)

Holistic approaches to memory solutions for the Autonomous Driving Era. - Daeyong Shim; Chunseok Jeong; Euncheol Lee; Junmo Kang; Seokcheol Yoon; Yongkee Kwon; Il Park 001; Hyun Ahn; Seonyong Cha; Jinkook Kim (ISCAS, 2022)

A High-Performance 1Tb 3b/Cell 3D-NAND Flash with a 194MB/s Write Throughput on over 300 Layers $ mathsf{i}$. - Bvunarvul Kim; Seungpil Lee; Beomseok Hah; Kanawoo Park; Yongsoon Park; Kangwook Jo; Yujong Noh; Hyeon-Cheon Seol; Hyunsoo Lee; Jae-Hyeon Shin; Seongjin Choi; Youngdon Jung; et al. (ISSCC, 2023)

Demonstration of crystalline IGZO transistor with high thermal stability for memory applications. - Whayoung Kim; Jaehyeon Kim; Dongjin Ko; Jun-Hwe Cha; Gyeongcheol Park; Youngbae Ahn; Jong-Young Lee; Minchul Sung; Hyejung Choi; Seung Wook Ryu; Seiyon Kim; Myung-Hee Na; et al. (VLSI Technology and Circuits, 2023)

The chalcogenide-based memory technology continues: beyond 20nm 4-deck 256Gb cross-point memory. - Jaeyun Yi; Myoungsub Kim; Jungwon Seo; Namkyun Park; Seungyun Lee; Jongil Kim; Gapsok Do; Hongjin Jang; Hyochol Koo; Sunglae Cho; Sujin Chae; Taehoon Kim; et al. (VLSI Technology and Circuits, 2023)

QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering. - Sunghyun Yoon; Sung-In Hong; Daehyun Kim; Garam Choi; Young Mo Kim; Kyunghoon Min; Seiyon Kim; Myung-Hee Na; Seonyong Cha (VLSI Technology and Circuits, 2023)

Realistic Noise-aware Training as a Component of the Holistic ACiM Development Platform. - Jihun Kim; Sangsu Park; Hongju Suh; Youngjae Kwon; Seonghun Lee; Yubin Lee; Kayoung Kim; Eungu Han; Jongil Kim; Kyu Sung Kim; Hyejung Choi; Seungwook Ryu; et al. (IMW, 2024)

Modeling and Demonstration for Multi-level Weight Conductance in Computational FeFET Memory Cell. - Won-Tae Koo; Jae-Gil Lee; Gunhee Lee; Woocheol Lee; Jungwook Woo; Dong Ik Suh; Joongsik Kim; Hyung Dong Lee; Seho Lee; Jaeyun Yi; Seonyong Cha (IMW, 2024)

Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays. - Youngjae Kwon; Won-Tae Koo; Sangsu Park; Dong Ik Suh; Gunhee Lee; Hyung Dong Lee; Youngbae Ahn; Dohee Kim; Seungwook Ryu; Hoseok Em; Seokjoon Kang; Chang Won Jeong; et al. (IMW, 2024)

First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory. - Myoungsub Kim; Yooncheol Bae; Jaehyuk Park; Jeongho Yeon; Hyungjoon Shim; Sehyun Jin; Hyunsoo Kim; Sangchul Oh; Gapsok Do; Dongyeol Yun; Hyung Dong Lee; David Ahn; et al. (VLSI Technology and Circuits, 2024)

30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681µm 1T-1MTJ Cross-Point Cell. - Kosuke Hatsuda; Katsuhiko Hoya; Ryosuke Takizawa; Fumiyoshi Matsuoka; Takaya Yasuda; Akira Katayama; Tadashi Miyakawa; Kazuyo Senju; Kazuki Okawa; Yuka Furukawa; Yu Shimada; Katsuya Kotake; et al. (ISSCC, 2025)