23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. - Kwangmyoung Rho; Kenji Tsuchida; Dongkeun Kim; Yutaka Shirai; Jihyae Bae; Tsuneo Inaba; Hiromi Noro; Hyunin Moon; Sungwoong Chung; Kazumasa Sunouchi; Jinwon Park; Kiseon Park; et al. (ISSCC, 2017)

First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory. - Myoungsub Kim; Yooncheol Bae; Jaehyuk Park; Jeongho Yeon; Hyungjoon Shim; Sehyun Jin; Hyunsoo Kim; Sangchul Oh; Gapsok Do; Dongyeol Yun; Hyung Dong Lee; David Ahn; et al. (VLSI Technology and Circuits, 2024)