Area Optimization of the Feed-Forward Equalizer for ADC-Based High-Speed Wireline Receiver Using Channel Characteristics. - Yujin Choi; Seoyoung Jang; Gain Kim (ICEIC, 2024)

A Study on the Effects of Power Loading Profile in Discrete Multitone Wireline Serial-Data Transceiver with Fixed-Point DSP-SerDes Simulator. - Seoyoung Jang; Jaewon Lee; Gain Kim (ICEIC, 2024)

DMT 3L4W: A 3-Lane 4-Wire Signaling With Discrete Multitone Modulation for High-Speed Wireline Chip-to-Chip Interconnects. - Seoyoung Jang; Jaewon Lee; Yujin Choi; Donggeon Kim; Gain Kim (ISCAS, 2024)

A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links. - Jaewon Lee; Seoyoung Jang; Yujin Choi; Donggeon Kim; Matthias Braendli; Marcel A. Kossel; Andrea Ruffino; Thomas Morf; Pier Andrea Francese; Gain Kim (ISCAS, 2024)

A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links. - Seoyoung Jang; Jaewon Lee; Yujin Choi; Donggeon Kim; Gain Kim (ISOCC, 2024)

A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links. - Jaewon Lee; Seoyoung Jang; Donggeon Kim; Yujin Choi; Sungyu Song; Gain Kim (ISOCC, 2024)

A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform. - Jaewon Lee; Seoyoung Jang; Yujin Choi; Donggeon Kim; Serdar A. Yonar; Matthias Braendli; Andrea Ruffino; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers. - Donggeon Kim; Yujin Choi; Jaewon Lee; Seoyoung Jang; Sungyu Song; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform. - Jaewon Lee; Seoyoung Jang; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation and Loading Profile Optimization on RFSoC. - Jaewon Lee; Seoyoung Jang; Donggeon Kim; Yujin Choi; Jong-Hyeok Yoon; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

7.5 A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath with Time-Based ADC in 5nm FinFET. - Jaewon Lee; Pier Andrea Francese; Matthias Brändli; Thomas Morf; Marcel A. Kossel; Seoyoung Jang; Gain Kim (ISSCC, 2025)

A 2-Lane DAC-/ADC-Based 2 × 2 MIMO PAM-4 MMSE-DFE Wireline Transceiver With FEXT Cancellation on RFSoC Platform. - Jaewon Lee; Seoyoung Jang; Yujin Choi; Donggeon Kim; Matthias Braendli; Thomas Morf; Marcel A. Kossel; Pier Andrea Francese; Gain Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)