A single chip VLSI architecture for a real time stereo vision processor. - Francis Jutand; Serge Maginot; Nicolas Demassieux; Henri Maître (ICASSP, 1988)

A general-purpose high-speed equalizer. - Serge Maginot; Freddy Balestro; Christophe Joanblanq; Patrice Senn; Jacques Palico (IEEE J. Solid State Circuits, 1991)

Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M. - Serge Maginot (EURO-DAC, 1992)

Lessons in Language Design: Cost/Benefit analysis of VHDL Features. - Oz Levia; Serge Maginot; Jacques Rouillard (DAC, 1994)

Non-reversible VHDL source-source encryption. - Kevin O'Brien; Serge Maginot (EURO-DAC, 1994)

Towards maximising the use of structural VHDL for synthesis. - Kevin O'Brien; Serge Maginot; Anne Robert (EURO-DAC, 1996)

Fast prototyping of memory models in VHDL for hardware emulation. - Kevin O'Brien; Serge Maginot (RSP, 1996)