Fault modelling and fault equivalence in CMOS technology. - Marie-Lise Flottes; Christian Landrault; Serge Pravossoudovitch (EURO-DAC, 1990)

Fault modeling and fault equivalence in CMOS technology. - Marie-Lise Flottes; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 1991)

A Novel Approach to Delay-Fault Diagnosis. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (DAC, 1992)

A New Reliable Method for Delay-Fault Diagnosis. - Marie-Lise Flottes; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (VLSI Design, 1992)

Delay-Fault Diagnosis by Critical-Path Tracing. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (IEEE Des. Test Comput., 1992)

An Implicit Delay-Fault Simulation Method with Approximate Detection Threshold Calculation. - D. Dumas; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ITC, 1993)

Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis. - D. Dumas; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (EDAC-ETC-EUROASIC, 1994)

A trace-based method for delay fault diagnosis in synchronous sequential circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (ED&TC, 1995)

Diagnostic of path and gate delay faults in non-scan sequential circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (VTS, 1995)

An advanced diagnostic method for delay faults in combinational faulty circuits. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 1995)

Delay fault diagnosis in sequential circuits based on path tracing. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (Integr., 1995)

DFSIM: A Gate-Delay Fault Simulator for Sequential Circuits. - P. Cavallera; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ED&TC, 1996)

A Diagnostic ATPG for Delay Faults Based on Genetic Algorithms. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; B. Rodriguez (ITC, 1996)

A new test pattern generation method for delay fault testing. - S. Cremoux; Christophe Fagot; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (VTS, 1996)

A gate resizing technique for high reduction in power consumption. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; D. Severac (ISLPED, 1997)

An optimized BIST test pattern generator for delay testing. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch (VTS, 1997)

A non-iterative gate resizing algorithm for high reduction in power consumption. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; D. Severac (Integr., 1997)

A BIST Structure to Test Delay Faults in a Scan Environment. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (Asian Test Symposium, 1998)

Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 1999)

A Test Vector Ordering Technique for Switching Activity Reduction During Test Operation. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Great Lakes Symposium on VLSI, 1999)

Low-energy BIST design: impact of the LFSR TPG parameters on the weighted switching activity. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Joan Figueras; Salvador Manich; João Paulo Teixeira 001; Marcelino B. Santos (ISCAS (1), 1999)

A Test Vector Inhibiting Technique for Low Energy BIST Design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (VTS, 1999)

A Scan-BIST Structure to Test Delay Faults in Sequential Circuits. - Patrick Girard 001; Christian Landrault; V. Moreda; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 1999)

An adjacency-based test pattern generator for low power BIST design. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2000)

Comparison between Random and Pseudo-Random Generation for BIST of Delay, Stuck-at and Bridging Faults. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (IOLTW, 2000)

Low power BIST design by hypergraph partitioning: methodology and architectures. - Patrick Girard 001; Christian Landrault; Loïs Guiller; Serge Pravossoudovitch (ITC, 2000)

Low Power BIST by Filtering Non-Detecting Vectors. - Salvador Manich; A. Gabarró; M. Lopez; Joan Figueras; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; João Paulo Teixeira 001; Marcelino B. Santos (J. Electron. Test., 2000)

A Gated Clock Scheme for Low Power Scan Testing of Logic ICs or Embedded Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (Asian Test Symposium, 2001)

Random Adjacent Sequences: An Efficient Solution for Logic BIST. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VLSI-SOC, 2001)

A Gated Clock Scheme for Low Power Scan-Based BIST. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (IOLTW, 2001)

A Modified Clock Scheme for a Low Power BIST Test Pattern Generator. - Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Hans-Joachim Wunderlich (VTS, 2001)

Delay Fault Testing: Choosing Between Random SIC and Random MIC Test Sequences. - Arnaud Virazel; René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2001)

Test Power: a Big Issue in Large SOC Designs. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (DELTA, 2002)

Power Driven Chaining of Flip-Flops in Scan Architectures. - Yannick Bonhomme; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (ITC, 2002)

On Using Efficient Test Sequences for BIST. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2002)

High Defect Coverage with Low-Power Test Sequences in a BIST Environment. - Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Hans-Joachim Wunderlich (IEEE Des. Test Comput., 2002)

Hardware Generation of Random Single Input Change Test Sequences. - René David; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2002)

Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address Decoders. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri (Asian Test Symposium, 2003)

Defect-oriented dynamic fault models for embedded-SRAMs. - Simone Borri; Magali Hage-Hassan; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (ETW, 2003)

Requirements for delay testing of look-up tables in SRAM-based FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (ETW, 2003)

Defect Analysis for Delay-Fault BIST in FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (IOLTS, 2003)

Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (ITC, 2003)

Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Bastian Hage-Hassan (Asian Test Symposium, 2004)

Design of Routing-Constrained Low Power Scan Chains. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2004)

High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (DELTA, 2004)

Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Bastian Hage-Hassan (ETS, 2004)

Manufacturing-oriented testing of delay faults in the logic architecture of symmetrical FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (ETS, 2004)

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (IOLTS, 2004)

March iC-: An Improved Version of March C- for ADOFs Detection. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri (VTS, 2004)

Power-Driven Routing-Constrained Scan Chain Design. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch (J. Electron. Test., 2004)

Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (DAC, 2005)

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian Hage-Hassan (ETS, 2005)

Controlling Peak Power Consumption During Scan Testing: Power-Aware DfT and Test Set Perspectives. - Nabil Badereddine; Patrick Girard 001; Arnaud Virazel; Serge Pravossoudovitch; Christian Landrault (PATMOS, 2005)

Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles. - Nabil Badereddine; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Christian Landrault (VLSI-SoC, 2005)

Data Retention Fault in SRAM Memories: Analysis and Detection Procedures. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian Hage-Hassan (VTS, 2005)

Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test. - Simone Borri; Magali Hage-Hassan; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2005)

Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Hage-Hassan (J. Electron. Test., 2005)

Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (J. Electron. Test., 2005)

Power-Aware Test Data Compression for Embedded IP Cores. - Nabil Badereddine; Zhanglei Wang; Patrick Girard 001; Krishnendu Chakrabarty; Serge Pravossoudovitch; Christian Landrault (ATS, 2006)

March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (DDECS, 2006)

Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing. - Nabil Badereddine; Patrick Girard 001; Serge Pravossoudovitch; Christian Landrault; Arnaud Virazel; Hans-Joachim Wunderlich (VLSI-SoC, 2006)

An Overview of Failure Mechanisms in Embedded Flash Memories. - Olivier Ginez; Jean Michel Daga; Marylene Combe; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2006)

A Gated Clock Scheme for Low Power Testing of Logic Cores. - Yannick Bonhomme; Patrick Girard 001; Loïs Guiller; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2006)

ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Simone Borri; Magali Bastian Hage-Hassan (J. Electron. Test., 2006)

An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. - Patrick Girard 001; Olivier Héron; Serge Pravossoudovitch; Michel Renovell (J. Electron. Test., 2006)

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior. - Magali Bastian; Vincent Gouin; Patrick Girard 001; Christian Landrault; Alexandre Ney; Serge Pravossoudovitch; Arnaud Virazel (ATS, 2007)

Fast Bridging Fault Diagnosis using Logic Information. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ATS, 2007)

Slow write driver faults in 65nm SRAM technology: analysis and March test solution. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (DATE, 2007)

A Mixed Approach for Unified Logic Diagnosis. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2007)

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ETS, 2007)

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (ETS, 2007)

DERRIC: A Tool for Unified Logic Diagnosis. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ETS, 2007)

A concurrent approach for testing address decoder faults in eFlash memories. - Olivier Ginez; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Jean Michel Daga (ITC, 2007)

Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2007)

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs. - Alexandre Ney; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (VTS, 2007)

Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits. - Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (J. Electron. Test., 2007)

A Design-for-Diagnosis Technique for SRAM Write Drivers. - Alexandre Ney; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian; Vincent Gouin (DATE, 2008)

SoC Symbolic Simulation: a case study on delay fault testing. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi (DDECS, 2008)

Improving Diagnosis Resolution without Physical Information. - Alexandre Rousset; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DELTA, 2008)

Using TMR Architectures for Yield Improvement. - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (DFT, 2008)

Yield Improvement, Fault-Tolerance to the Rescue?. - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (IOLTS, 2008)

A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. - Alexandre Ney; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (ITC, 2008)

SoC Yield Improvement: Redundant Architectures to the Rescue? - Julien Vial; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (ITC, 2008)

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing. - Alexandre Ney; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian; Vincent Gouin (VTS, 2008)

A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction. - Nabil Badereddine; Zhanglei Wang; Patrick Girard 001; Krishnendu Chakrabarty; Arnaud Virazel; Serge Pravossoudovitch; Christian Landrault (J. Electron. Test., 2008)

Delay Fault Diagnosis in Sequential Circuits. - Youssef Benabboud; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Olivia Riewer (Asian Test Symposium, 2009)

A new design-for-test technique for SRAM core-cell stability faults. - Alexandre Ney; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian; Vincent Gouin (DATE, 2009)

Comprehensive bridging fault diagnosis based on the SLAT paradigm. - Youssef Benabboud; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Laroussi Bouzaida; Isabelle Izaute (DDECS, 2009)

An efficient fault simulation technique for transition faults in non-scan sequential circuits. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi; Matteo Sonza Reorda (DDECS, 2009)

A case study on logic diagnosis for System-on-Chip. - Youssef Benabboud; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Laroussi Bouzaida; Isabelle Izaute (ISQED, 2009)

NAND flash testing: A preliminary study on actual defects. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard (ITC, 2009)

A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash. - Olivier Ginez; Jean Michel Daga; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch; Arnaud Virazel (J. Electron. Test., 2009)

Is triple modular redundancy suitable for yield improvement? - Julien Vial; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Christian Landrault; Serge Pravossoudovitch (IET Comput. Digit. Tech., 2009)

Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. - Alexandre Ney; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Magali Bastian (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A Comprehensive System-on-Chip Logic Diagnosis. - Youssef Benabboud; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Olivia Riewer (Asian Test Symposium, 2010)

A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. - Paolo Rech; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Luigi Dilillo (Asian Test Symposium, 2010)

A statistical simulation method for reliability analysis of SRAM core-cells. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (DAC, 2010)

Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. - Fangmei Wu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Junxia Ma; Wei Zhao 010; Mohammad Tehranipoor; Xiaoqing Wen (DDECS, 2010)

An Exact and Efficient Critical Path Tracing Algorithm. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Paolo Bernardi; Matteo Sonza Reorda (DELTA, 2010)

Impact of Resistive-Bridging Defects in SRAM Core-Cell. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (DELTA, 2010)

Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (ETS, 2010)

Setting test conditions for improving SRAM reliability. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (ETS, 2010)

A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (ETS, 2010)

Parity prediction synthesis for nano-electronic gate designs. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (ITC, 2010)

Is test power reduction through X-filling good enough? - Fangmei Wu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Mohammad Tehranipoor; Kohei Miyase; Xiaoqing Wen; Nisar Ahmed (ITC, 2010)

Detecting NBTI induced failures in SRAM core-cells. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (VTS, 2010)

A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. - Fangmei Wu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Mohammad Tehranipoor; Xiaoqing Wen; Nisar Ahmed (J. Low Power Electron., 2010)

A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. - Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (IEEE Trans. Computers, 2010)

A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (Asian Test Symposium, 2011)

Failure Analysis and Test Solutions for Low-Power SRAMs. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri; Arnaud Virazel; Nabil Badereddine (Asian Test Symposium, 2011)

On using a SPICE-like TSTAC™ eFlash model for design and test. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (DDECS, 2011)

A study of path delay variations in the presence of uncorrelated power and ground supply noise. - Aida Todri; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2011)

Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. - Leonardo Bonet Zordan; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (DDECS, 2011)

On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. - Paolo Bernardi; Matteo Sonza Reorda; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch (DFT, 2011)

Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. - Luigi Dilillo; Alberto Bosio; Miroslav Valka; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (DFT, 2011)

A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. - Miroslav Valka; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Ernesto Sánchez 001; Mauricio de Carvalho; Matteo Sonza Reorda (ETS, 2011)

On using address scrambling to implement defect tolerance in SRAMs. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (ITC, 2011)

Advanced test methods for SRAMs. - Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (VTS, 2012)

Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. - Renan Alves Fonseca; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Nabil Badereddine (J. Electron. Test., 2012)

Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTACTM eFlash Memories. - Pierre-Didier Mauroux; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Benoît Godard; Gilles Festes; Laurent Vachez (J. Electron. Test., 2012)

On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. - Elena I. Vatajelu; Georgios Tsiligiannis; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri; Arnaud Virazel; Frederic Wrobel; Frédéric Saigné (DFTS, 2013)

SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. - Georgios Tsiligiannis; Elena I. Vatajelu; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri; Arnaud Virazel; Frederic Wrobel; Frédéric Saigné (IOLTS, 2013)

Characterization of an SRAM based particle detector for mixed-field radiation environments. - Georgios Tsiligiannis; Luigi Dilillo; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Aida Todri-Sanial; Arnaud Virazel; Julien Mekki; Markus Brugger; J.-R. Vaillé; Frederic Wrobel; Frédéric Saigné (IWASI, 2013)

Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. - Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (NEWCAS, 2013)

Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. - Anu Asokan; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (DDECS, 2014)

A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. - Anu Asokan; Aida Todri-Sanial; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel (ISVLSI, 2014)

Intra-Cell Defects Diagnosis. - Zhenzhou Sun; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Arnaud Virazel; Etienne Auvray (J. Electron. Test., 2014)

A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. - D. A. Tran; Arnaud Virazel; Alberto Bosio; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch; Hans-Joachim Wunderlich (J. Electron. Test., 2014)

An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. - Anu Asokan; Alberto Bosio; Arnaud Virazel; Luigi Dilillo; Patrick Girard 001; Serge Pravossoudovitch (ISVLSI, 2015)

A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. - Imran Wali; Arnaud Virazel; Alberto Bosio; Patrick Girard 001; Serge Pravossoudovitch; Matteo Sonza Reorda (J. Electron. Test., 2016)

Is aproximate computing suitable for selective hardening of arithmetic circuits? - Bastien Deveautour; Arnaud Virazel; Patrick Girard 001; Serge Pravossoudovitch; Valentin Gherman (DTIS, 2018)