ASIC synthesis of a flexible 80 Mbit/s Reed-Solomon Codec. - Koen Van Nieuwenhove; Kjell Cools; D. Devisch; Ivo Bolsens; Serge Vernalde; Kim Chansik; R. B. W. Lee; Oh Younguk (EURO-DAC, 1994)

Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis. - Elisabeth Berrebi; Polen Kission; Serge Vernalde; S. De Troch; Jean-Claude Herluison; Jean Fréhel; Ahmed Amine Jerraya; Ivo Bolsens (DAC, 1996)

A Hilbert fractal codec for region oriented compression of color images. - Jan Bormans; Serge Vernalde; Jan Cornelis 001; Ivo Bolsens; Hugo De Man (ICECS, 1996)

Highly scalable parallel parametrizable architecture of the motion estimator. - Radim Cmar; Serge Vernalde (ED&TC, 1997)

Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications. - Patrick Schaumont; Serge Vernalde; Luc Rijnders; Marc Engels; Ivo Bolsens (ED&TC, 1997)

A Programming Environment for the Design of Complex High Speed ASICs. - Patrick Schaumont; Serge Vernalde; Luc Rijnders; Marc Engels; Ivo Bolsens (DAC, 1998)

A Technique for Combined Virtual Prototyping and Hardware Design. - Patrick Schaumont; Geert Vanmeerbeeck; E. Watzeels; Serge Vernalde; Marc Engels; Ivo Bolsens (International Workshop on Rapid System Prototyping, 1998)

Low Power Digital Frequency Conversion Architectures. - Patrick Schaumont; Serge Vernalde; Marc Engels; Ivo Bolsens (J. VLSI Signal Process., 1998)

A 10 Mbit/s Upstream Cable Modem with Automatic equalization. - Patrick Schaumont; Radim Cmar; Serge Vernalde; Marc Engels (DAC, 1999)

Hardware Reuse at the Behavioral Level. - Patrick Schaumont; Radim Cmar; Serge Vernalde; Marc Engels; Ivo Bolsens (DAC, 1999)

A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement. - Radim Cmar; Luc Rijnders; Patrick Schaumont; Serge Vernalde; Ivo Bolsens (DATE, 1999)

A new algorithm for elimination of common subexpressions. - Robert Pasko; Patrick Schaumont; Veerle Derudder; Serge Vernalde; Daniela Duracková (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Functional verification of an embedded network component by co-simulation with a real network. - Robert Pasko; Radim Cmar; Patrick Schaumont; Serge Vernalde (HLDVT, 2000)

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. - Yajun Ha; Serge Vernalde; Patrick Schaumont; Marc Engels; Hugo De Man (PDPTA, 2000)

A Hardware Virtual Machine for the Networked Reconfiguration. - Yajun Ha; Patrick Schaumont; Marc Engels; Serge Vernalde; Freddy Potargent; Luc Rijnders; Hugo De Man (IEEE International Workshop on Rapid System Prototyping, 2000)

Virtual Java/FPGA interface for networked reconfiguration. - Yajun Ha; Geert Vanmeerbeeck; Patrick Schaumont; Serge Vernalde; Marc Engels; Rudy Lauwereins; Hugo De Man (ASP-DAC, 2001)

Platform design approach for re-configurable network appliances. - Radim Cmar; Robert Pasko; Jean-Yves Mignolet; Geert Vanmeerbeeck; Patrick Schaumont; Serge Vernalde (CICC, 2001)

Hardware/software partitioning of embedded system in OCAPI-xl. - Geert Vanmeerbeeck; Patrick Schaumont; Serge Vernalde; Marc Engels; Ivo Bolsens (CODES, 2001)

A SW/HW Interface API for Java/FPGA Co-Designed Applets. - Yajun Ha; Patrick Schaumont; Serge Vernalde; Marc Engels; Rudy Lauwereins; Hugo De Man (FCCM, 2001)

Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. - Yajun Ha; Bingfeng Mei; Patrick Schaumont; Serge Vernalde; Rudy Lauwereins; Hugo De Man (FPL, 2001)

High-performance flexible all-digital quadrature up and down converter chip. - Robert Pasko; Luc Rijnders; Patrick R. Schaumont; Serge A. Vernalde; Daniela Duracková (IEEE J. Solid State Circuits, 2001)

Techniques to Evolve a C++ Based System Design Language. - Robert Pasko; Serge Vernalde; Patrick Schaumont (DATE, 2002)

Adding Hardware Support to the HotSpot Virtual Machine for Domain Specific Applications. - Yajun Ha; Radovan Hipik; Serge Vernalde; Diederik Verkest; Marc Engels; Rudy Lauwereins; Hugo De Man (FPL, 2002)

Interconnection Networks Enable Fine-Grain Dynamic Multi-tasking on FPGAs. - Théodore Marescaux; T. Andrei Bartic; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (FPL, 2002)

DRESC: a retargetable compiler for coarse-grained reconfigurable architectures. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (FPT, 2002)

Building a Virtual Framework for Networked Reconfigurable Hardware and Software Objects. - Yajun Ha; Serge Vernalde; Patrick Schaumont; Marc Engels; Rudy Lauwereins; Hugo De Man (J. Supercomput., 2002)

Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (DATE, 2003)

Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip. - Jean-Yves Mignolet; Vincent Nollet; Paul Coene; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (DATE, 2003)

Hierarchical Run-Time Reconfiguration Managed by an Operating System for Reconfigurable Systems. - Vincent Nollet; Jean-Yves Mignolet; T. Andrei Bartic; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (Engineering of Reconfigurable Systems and Algorithms, 2003)

Run-Time Scheduling for Multimedia Applications on Dynamically Reconfigurable Systems. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (ESTIMedia, 2003)

Application of Task Concurrency Management on Dynamically Reconfigurable Hardware Platforms. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (FCCM, 2003)

Networks on Chip as Hardware Components of an OS for Reconfigurable Systems. - Théodore Marescaux; Jean-Yves Mignolet; T. Andrei Bartic; W. Moffat; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (FPL, 2003)

ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Hugo De Man; Rudy Lauwereins (FPL, 2003)

Run-Time Minimization of Reconfiguration Overhead in Dynamically Reconfigurable Systems. - Javier Resano; Daniel Mozos; Diederik Verkest; Serge Vernalde; Francky Catthoor (FPL, 2003)

Flexible system model and architectural exploration for HIPERLAN 2 DLC wireless LAN protocol. - Vivek Nema; Bart van Poucke; Miguel Glassee; Serge Vernalde (ICC, 2003)

A framework for mapping scalable networked applications on run-time reconfigurable platforms. - Nam Pham Ngoc 001; Gauthier Lafruit; Jean-Yves Mignolet; Serge Vernalde; Geert Deconinck; Rudy Lauwereins (ICME, 2003)

Designing an Operating System for a Heterogeneous Reconfigurable So. - Vincent Nollet; Paul Coene; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (IPDPS, 2003)

Highly scalable network on chip for reconfigurable systems. - T. Andrei Bartic; Jean-Yves Mignolet; Vincent Nollet; Théodore Marescaux; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (SoC, 2003)

Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. - Richard Stahl; Robert Pasko; Luc Rijnders; Diederik Verkest; Serge Vernalde; Rudy Lauwereins; Francky Catthoor (SCOPES, 2003)

Operating-system controlled network on chip. - Vincent Nollet; Théodore Marescaux; Diederik Verkest; Jean-Yves Mignolet; Serge Vernalde (DAC, 2004)

Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study. - Bingfeng Mei; Serge Vernalde; Diederik Verkest; Rudy Lauwereins (DATE, 2004)

Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. - T. Andrei Bartic; Dirk Desmet; Jean-Yves Mignolet; Théodore Marescaux; Diederik Verkest; Serge Vernalde; Rudy Lauwereins; J. Miller; Frédéric Robert (FPL, 2004)

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays. - Steven J. E. Wilton; Noha Kafafi; Bingfeng Mei; Serge Vernalde (FPT, 2004)

Run-time support for heterogeneous multitasking on reconfigurable SoCs. - Théodore Marescaux; Vincent Nollet; Jean-Yves Mignolet; T. Andrei Bartic; W. Moffat; Prabhat Avasare; Paul Coene; Diederik Verkest; Serge Vernalde; Rudy Lauwereins (Integr., 2004)

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. - Javier Resano; Diederik Verkest; Daniel Mozos; Serge Vernalde; Francky Catthoor (Microprocess. Microsystems, 2004)