Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs. - Jaan Raik; Raimund Ubar; Sergei Devadze; Artur Jutman (EDCC, 2005)

Fault Simulation with Parallel Critical Path Tracing for Combinatorial Circuits Using Structurally Synthesized BDDs. - Sergei Devadze; Jaan Raik; Artur Jutman; Raimund Ubar (LATW, 2006)

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ETS, 2007)

Learning Digital Test and Diagnostics via Internet. - Raimund Ubar; Artur Jutman; Margus Kruus; Elmet Orasson; Sergei Devadze; Heinz-Dietrich Wuttke (Int. J. Online Eng., 2007)

Parallel fault backtracing for calculation of fault coverage. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (ASP-DAC, 2008)

Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance. - Raimund Ubar; Sergei Devadze; Maksim Jenihhin; Jaan Raik; Gert Jervan; Peeter Ellervee (DELTA, 2008)

Fast extended test access via JTAG and FPGAs. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (ITC, 2009)

Turning JTAG inside out for fast extended test access. - Sergei Devadze; Artur Jutman; Igor Aleksejev; Raimund Ubar (LATW, 2009)

Parallel X-fault simulation with critical path tracing technique. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DATE, 2010)

Fast Fault Simulation for Extended Class of Faults in Scan Path Circuits. - Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DELTA, 2010)

Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. - Dmitri Mironov; Raimund Ubar; Sergei Devadze; Jaan Raik; Artur Jutman (DSD, 2010)

Testing beyond the SoCs in a lego style. - Anton Tsertov; Artur Jutman; Sergei Devadze (EWDTS, 2010)

Collaborative Distributed Fault Simulation for Digital Electronic Circuits. - Eero Ivask; Sergei Devadze; Raimund Ubar (IDC, 2010)

Collaborative Distributed Computing in the Field of Digital Electronics Testing. - Eero Ivask; Sergei Devadze; Raimund Ubar (BASYS, 2010)

Automatic SoC Level Test Path Synthesis Based on Partial Functional Models. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (Asian Test Symposium, 2011)

SoC and Board Modeling for Processor-Centric Board Testing. - Anton Tsertov; Raimund Ubar; Artur Jutman; Sergei Devadze (DSD, 2011)

Invited paper: System-wide fault management based on IEEE P1687 IJTAG. - Artur Jutman; Sergei Devadze; Igor Aleksejev (ReCoSoC, 2011)

Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits. - Eero Ivask; Sergei Devadze; Raimund Ubar (Scalable Comput. Pract. Exp., 2011)

Embedded synthetic instruments for Board-Level testing. - Artur Jutman; Sergei Devadze; Igor Aleksejev; Thomas Wenzel (ETS, 2012)

FPGA-based synthetic instrumentation for board test. - Igor Aleksejev; Artur Jutman; Sergei Devadze; Sergei Odintsov; Thomas Wenzel (ITC, 2012)

On in-system programming of non-volatile memories. - Anton Tsertov; Sergei Devadze; Artur Jutman; Artjom Jasnetski (MIXDES, 2013)

At-speed self-testing of high-performance pipe-lined processing architectures. - Maksim Gorev; Raimund Ubar; Peeter Ellervee; Sergei Devadze; Jaan Raik; Mart Min (NORCHIP, 2013)

Effective Scalable IEEE 1687 Instrumentation Network for Fault Management. - Artur Jutman; Sergei Devadze; Konstantin Shibin (IEEE Des. Test, 2013)

Design, Verification, and Application of IEEE 1687. - Farrokh Ghani Zadegan; Erik Larsson; Artur Jutman; Sergei Devadze; Rene Krenz-Baath (ATS, 2014)

Critical Path Tracing Based Simulation of Transition Delay Faults. - Jaak Kousaar; Raimund Ubar; Sergei Devadze; Jaan Raik (DSD, 2014)

Asynchronous Fault Detection in IEEE P1687 Instrument Network. - Konstantin Shibin; Sergei Devadze; Artur Jutman (NATW, 2014)

Fault simulation with parallel exact critical path tracing in multiple core environment. - Maksim Gorev; Raimund Ubar; Sergei Devadze (DATE, 2015)

Combinational fault simulation in sequential circuits. - Raimund Ubar; Jaak Kousaar; Maksim Gorev; Sergei Devadze (ISCAS, 2015)

Virtual reconfigurable scan-chains on FPGAs for optimized board test. - Igor Aleksejev; Sergei Devadze; Artur Jutman; Konstantin Shibin (LATS, 2015)

Functional self-test of high-performance pipe-lined signal processing architectures. - Maksim Gorev; Raimund Ubar; Peeter Ellervee; Sergei Devadze; Jaan Raik; Mart Min (Microprocess. Microsystems, 2015)

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra. - Jaak Kousaar; Raimund Ubar; Sergei Devadze; Jaan Raik (Microprocess. Microsystems, 2015)

On coverage of timing related faults at board level. - Artur Jutman; Igor Aleksejev; Sergei Devadze (ETS, 2016)

Designing reliable cyber-physical systems overview associated to the special session at FDL'16. - Gadi Aleksandrowicz; Eli Arbel; Roderick Bloem; Timon D. ter Braak; Sergei Devadze; Görschwin Fey; Maksim Jenihhin; Artur Jutman; Hans G. Kerkhoff; Robert Könighofer; Jan Malburg; Shiri Moran; et al. (FDL, 2016)

A suite of IEEE 1687 benchmark networks. - Anton Tsertov; Artur Jutman; Sergei Devadze; Matteo Sonza Reorda; Erik Larsson; Farrokh Ghani Zadegan; Riccardo Cantoro; Mehrdad Montazeri; Rene Krenz-Baath (ITC, 2016)

On-line fault classification and handling in IEEE1687 based fault management system for complex SoCs. - Konstantin Shibin; Sergei Devadze; Artur Jutman (LATS, 2016)

Optimization of Boundary Scan Tests Using FPGA-Based Efficient Scan Architectures. - Igor Aleksejev; Sergei Devadze; Artur Jutman; Konstantin Shibin (J. Electron. Test., 2016)

Marginal PCB assembly defect detection on DDR3/4 memory bus. - Sergei Odintsov; Artur Jutman; Sergei Devadze (ITC, 2017)

Health Management for Self-Aware SoCs Based on IEEE 1687 Infrastructure. - Konstantin Shibin; Sergei Devadze; Artur Jutman; Martin Grabmann; Robin Pricken (IEEE Des. Test, 2017)

Run-time reconfigurable instruments for advanced board-level testing. - Igor Aleksejev; Artur Jutman; Sergei Devadze (IEEE Instrum. Meas. Mag., 2017)

Parallel Critical Path Tracing Fault Simulation in Sequential Circuits. - Jaak Kousaar; Raimund Ubar; Sergei Kostin; Sergei Devadze; Jaan Raik (MIXDES, 2018)

Hierarchical Timing-Critical Paths Analysis in Sequential Circuits. - Lembit Jurimagi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Sergei Kostin (PATMOS, 2018)

Application Specific True Critical Paths Identification in Sequential Circuits. - Lembit Jürimägi; Raimund Ubar; Maksim Jenihhin; Jaan Raik; Sergei Devadze; Adeboye Stephen Oyeniran (IOLTS, 2019)

HLS-based Optimization of Tau Triggering Algorithm for LHC: a case study. - Natalia Cherezova; Dmitri Mihhailov; Sergei Devadze; Artur Jutman (CoRR, 2022)

On-Chip Sensors Data Collection and Analysis for SoC Health Management. - Konstantin Shibin; Maksim Jenihhin; Artur Jutman; Sergei Devadze; Anton Tsertov (DFT, 2023)

Keynote: Cost-Efficient Reliability for Edge-AI Chips. - Maksim Jenihhin; Mahdi Taheri; Natalia Cherezova; Mohammad Hasan Ahmadilivani; Hardi Selg; Artur Jutman; Konstantin Shibin; Anton Tsertov; Sergei Devadze; Rama Mounika Kodamanchili; Ahsan Rafiq; Jaan Raik; et al. (LATS, 2024)

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis. - Sergei Devadze; Christine Elizabeth Nielsen; Dmitri Mihhailov; Peeter Ellervee (NorCAS, 2024)