Investigation and Design of a Threshold element for the Fault Self-Timed Circuits. - Anton N. Kamenskih; Sergey F. Tyurin (DESSERT, 2019)

A Quad CMOS Gates Checking method. - Sergey F. Tyurin (Int. J. Comput., 2019)

Reversible Majority Voter Based on Fredkin Gates. - Sergey F. Tyurin (DESSERT, 2020)

The Fault Tolerant Černý Finite State Machine: a Concept and VHDL Models. - Vyacheslav Kharchenko; Sergey F. Tyurin; Herman Fesenko; Oleg Goncharovskij (IDAACS, 2021)

Self-Timed FPGA Design Perspectives. - Sofya K. Chikarenko; Kseniya M. Ivanova; Alexandra Yu. Skornyakova; Sergey F. Tyurin (IDT, 2021)

A Decoder - Look up Tables for FPGAs. - Sergey F. Tyurin; Ruslan V. Vikhorev (Int. J. Comput., 2021)