Sergey Y. Shumarayev

According to our database1, Sergey Y. Shumarayev authored at least 15 papers between 2002 and 2023.

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Bibliography

2023
Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm<sup>2</sup> AIB 2.0 Interface to Provide Versatile Workload Acceleration.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2022

Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

2021

2020
TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O.
IEEE Micro, 2020

2018
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2015

2013
A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012
On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing.
Proceedings of the 2012 IEEE International Test Conference, 2012

2010
Introducing 28-nm stratix VFPGAs: Built for bandwidth.
Proceedings of the 2010 IEEE Hot Chips 22 Symposium, Stanford, CA, USA, August 22-24, 2010, 2010

2009
Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007
Receiver Offset Cancellation in 90-nm PLD Integrated SERDES.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005
A signal integrity-based link performance simulation platform.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2002
Interconnect enhancements for a high-speed PLD architecture.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002


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