A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop. - Woogeun Rhee; Herschel A. Ainspan; Sergey V. Rylov; Alexander V. Rylyakov; Michael P. Beakes; Daniel J. Friedman; Sudhir M. Gowda; Mehmet Soyuer (CICC, 2003)

10+ Gb/s 90nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (CICC, 2004)

A 10-Gb/s two-dimensional eye-opening monitor in 0.13-μm standard CMOS. - Behnam Analui; Alexander V. Rylyakov; Sergey V. Rylov; Mounir Meghelli; Ali Hajimiri (IEEE J. Solid State Circuits, 2005)

10+ gb/s 90-nm CMOS serial link demo in CBGA package. - Sergey V. Rylov; Scott K. Reynolds; Daniel W. Storaska; Brian A. Floyd; Mohit Kapur; Thomas Zwick; Sudhir M. Gowda; Michael Sorna (IEEE J. Solid State Circuits, 2005)

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. - Mounir Meghelli; Sergey V. Rylov; John F. Bulzacchelli; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; L. Shan; et al. (ISSCC, 2006)

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology. - John F. Bulzacchelli; Mounir Meghelli; Sergey V. Rylov; Woogeun Rhee; Alexander V. Rylyakov; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Aichin Chung; Troy J. Beukema; Petar K. Pepeljugoski; Lei Shan; et al. (IEEE J. Solid State Circuits, 2006)

A 2.6mW 370MHz-to-2.5GHz Open-Loop Quadrature Clock Generator. - Kyu-Hyoun Kim; Paul W. Coteus; Daniel M. Dreps; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2008)

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS. - John F. Bulzacchelli; Timothy O. Dickson; Zeynep Toprak Deniz; Herschel A. Ainspan; Benjamin D. Parker; Michael P. Beakes; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

A 5.4mW 0.0035mm2 0.48psrms-jitter 0.8-to-5GHz non-PLL/DLL all-digital phase generator/rotator in 45nm SOI CMOS. - Kyu-Hyoun Kim; Daniel M. Dreps; Frank D. Ferraiolo; Paul W. Coteus; Seongwon Kim; Sergey V. Rylov; Daniel J. Friedman (ISSCC, 2009)

An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz. - Montek Singh; José A. Tierno; Alexander V. Rylyakov; Sergey V. Rylov; Steven M. Nowick (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A 28Gb/s 4-tap FFE/15-tap DFE serial link transceiver in 32nm SOI CMOS technology. - John F. Bulzacchelli; Troy J. Beukema; Daniel W. Storaska; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Christian Menolfi; David Hanson; Juergen Hertle; Thomas Morf; et al. (ISSCC, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Bing Dang; Cornelia K. Tsang; Paul S. Andry; John F. Bulzacchelli; Herschel A. Ainspan; Xiaoxiong Gu; Lavanya Turlapati; Michael P. Beakes; Benjamin D. Parker; et al. (IEEE J. Solid State Circuits, 2012)

A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology. - Gautam R. Gangasani; Chun-Ming Hsu; John F. Bulzacchelli; Sergey V. Rylov; Troy J. Beukema; David Freitas; William R. Kelly; Michael Shannon; Jieming Qi; Hui H. Xu; Joseph Natonio; Todd M. Rasmus; et al. (IEEE J. Solid State Circuits, 2012)

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Christian W. Baks; et al. (CICC, 2014)

22.1 A 25Gb/s burst-mode receiver for rapidly reconfigurable optical networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (ISSCC, 2015)

A 25 Gb/s burst-mode receiver for low latency photonic switch networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Clint Schow; Mounir Meghelli (OFC, 2015)

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Ankur Agrawal; Seongwon Kim; Ping-Hsuan Hsieh; John F. Bulzacchelli; Mark A. Ferriss; Herschel A. Ainspan; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; et al. (IEEE J. Solid State Circuits, 2015)

A 25 Gb/s Burst-Mode Receiver for Low Latency Photonic Switch Networks. - Alexander V. Rylyakov; Jonathan E. Proesel; Sergey V. Rylov; Benjamin G. Lee; John F. Bulzacchelli; Abhijeet Ardey; Benjamin D. Parker; Michael P. Beakes; Christian W. Baks; Clint Schow; Mounir Meghelli (IEEE J. Solid State Circuits, 2015)

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. - Sergey V. Rylov; Troy J. Beukema; Zeynep Toprak Deniz; Thomas Toifl; Yong Liu 023; Ankur Agrawal; Peter Buchmann; Alexander V. Rylyakov; Michael P. Beakes; Benjamin D. Parker; Mounir Meghelli (ISSCC, 2016)

A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS. - Jonathan E. Proesel; Zeynep Toprak Deniz; Alessandro Cevrero; Ilter Özkaya; Seongwon Kim; Daniel M. Kuchta; Sungjae Lee 005; Sergey V. Rylov; Herschel A. Ainspan; Timothy O. Dickson; John F. Bulzacchelli; Mounir Meghelli (IEEE J. Solid State Circuits, 2018)

An 8-bit 56GS/s 64x Time-Interleaved ADC with Bootstrapped Sampler and Class-AB Buffer in 4nm CMOS. - Serdar S. Yonar; Pier Andrea Francese; Matthias Brändli; Marcel A. Kossel; Thomas Morf; Jonathan E. Proesel; Sergey V. Rylov; Herschel A. Ainspan; Martin Cochet; Zeynep Toprak Deniz; Timothy O. Dickson; Troy J. Beukema; et al. (VLSI Technology and Circuits, 2022)

A Switched-Capacitor Integer Compute Unit with Decoupled Storage and Arithmetic for Cloud AI Inference in 5nm CMOS. - Ankur Agrawal; Monodeep Kar; Kyu-Hyoun Kim; Sergey V. Rylov; Jinwook Jung; Seiji Munetoh; Kohji Hosokawa; Xin Zhang 025; Bahman Hekmatshoartabari; Fabio Carta; Martin Cochet; Robert Casatuta; et al. (VLSI Technology and Circuits, 2023)