Interconnect enhancements for a high-speed PLD architecture. - Michael D. Hutton; Vinson Chan; Peter Kazarian; Victor Maruri; Tony Ngai; Jim Park; Rakesh H. Patel; Bruce Pedersen; Jay Schleicher; Sergey Y. Shumarayev (FPGA, 2002)

A signal integrity-based link performance simulation platform. - Yuming Tao; William Bereza; Rakesh H. Patel; Sergey Y. Shumarayev; Tad A. Kwasniewski (CICC, 2005)

Receiver Offset Cancellation in 90-nm PLD Integrated SERDES. - Simar Maangat; Toan Nguyen; Wilson Wong; Sergey Y. Shumarayev; Tina Tran; Tim Hoang; Richard Cliff (CICC, 2007)

Emerging standards at ∼10 Gbps for wireline communications and associated integrated circuit design and validation. - Mike Peng Li; Sergey Y. Shumarayev (CICC, 2009)

Introducing 28-nm stratix VFPGAs: Built for bandwidth. - Dan Mansur; Sergey Y. Shumarayev (Hot Chips Symposium, 2010)

On-die instrumentation to solve challenges for 28nm, 28Gbps timing variability and stressing. - Weichi Ding; Mingde Pan; Wilson Wong; Daniel Chow; Mike Peng Li; Sergey Y. Shumarayev (ITC, 2012)

A 3.1mW phase-tunable quadrature-generation method for CEI 28G short-reach CDR in 28nm CMOS. - Kanupriya Bhardwaj; Sriram Narayan; Sergey Y. Shumarayev; Thomas H. Lee (ISSCC, 2013)

Arria™ 10 device architecture. - Jeffrey Tyhach; Mike Hutton; Sean Atsatt; Arifur Rahman; Brad Vest; David M. Lewis; Martin Langhammer; Sergey Y. Shumarayev; Tim Hoang; Allen Chan; Dong-Myung Choi; Dan Oh; et al. (CICC, 2015)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only). - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Sergey Y. Shumarayev; Aravind Dasu (FPGA, 2018)

In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC. - Eriko Nurvitadhi; Jeffrey J. Cook; Asit K. Mishra; Debbie Marr; Kevin Nealis; Philip Colangelo; Andrew C. Ling; Davor Capalija; Utku Aydonat; Aravind Dasu; Sergey Y. Shumarayev (FPL, 2018)

TeraPHY: A Chiplet Technology for Low-Power, High-Bandwidth In-Package Optical I/O. - Mark T. Wade; Roy Meade; Chandru Ramamurthy; Michael Rust; Forrest Sedgwick; Vladimir Stojanovic; Derek Van Orden; Chong Zhang; Chen Sun 003; Sergey Y. Shumarayev; Conor O'Keeffe; Erik Anderson; et al. (IEEE Micro, 2020)

8 Tbps Co-Packaged FPGA and Silicon Photonics Optical IO. - Kaveh Hosseini; Edwin Kok; Sergey Y. Shumarayev; Chia-Pin Chiu; Arnab Sarkar 004; Asako Toda; Yanjing Ke; Allen Chan; Daniel Jeong; Mason Zhang; Sangeeta Raman; Thungoc Tran; et al. (OFC, 2021)

Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF Applications. - Sergey Y. Shumarayev; Allen Chan; Tim Hoang; Robert Keller (HCS, 2022)

5.12 Tbps Co-Packaged FPGA and Silicon Photonics Interconnect I/O. - Kaveh Hosseini; Edwin Kok; Sergey Y. Shumarayev; Daniel Jeong; Allen Chan; Austin Katzin; Songtao Liu; Radek Roucka; Manan Raval; Minh Mac; Chia-Pin Chiu; Thungoc Tran; et al. (VLSI Technology and Circuits, 2022)

Arvon: A Heterogeneous SiP Integrating a 14nm FPGA and Two 22nm 1.8TFLOPS/W DSPs with 1.7Tbps/mm2 AIB 2.0 Interface to Provide Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (VLSI Technology and Circuits, 2023)

Silicon Photonics Chip I/O for Ultra High-Bandwidth and Energy-Efficient Die-to-Die Connectivity. - Yuyang Wang 003; Songli Wang; Robert Parsons; Asher Novick; Vignesh Gopal; Kaylx Jang; Anthony Rizzo; Chia-Pin Chiu; Kaveh Hosseini; Tim Tri Hoang; Sergey Y. Shumarayev; Keren Bergman (CICC, 2024)

Arvon: A Heterogeneous System-in-Package Integrating FPGA and DSP Chiplets for Versatile Workload Acceleration. - Wei Tang 010; Sung-Gun Cho; Tim Tri Hoang; Jacob Botimer; Wei Qiang Zhu; Ching-Chi Chang; Cheng-Hsun Lu; Junkang Zhu; Yaoyu Tao; Tianyu Wei; Naomi Kavi Motwani; Mani Yalamanchi; et al. (IEEE J. Solid State Circuits, 2024)