Some Notes on Power Management on FPGA-Based Systems. - Eduardo I. Boemo; Guillermo González de Rivera; Sergio López-Buedo; Juan M. Meneses (FPL, 1995)

The Wave Pipeline Effect on LUT-Based FPGA Architectures. - Eduardo I. Boemo; Sergio López-Buedo; Juan M. Meneses (FPGA, 1996)

Thermal monitoring on FPGAs using ring-oscillators. - Eduardo I. Boemo; Sergio López-Buedo (FPL, 1997)

Some experiments about wave pipelining on FPGA's. - Eduardo I. Boemo; Sergio López-Buedo; Juan M. Meneses (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A biologically inspired autonomous robot that learns approach-avoidance behaviors. - Luis Fernando Lago-Fernández; Manuel A. Sánchez-Montañés; Sergio López-Buedo (Agents, 2000)

Thermal Testing on Reconfigurable Computers. - Sergio López-Buedo; Javier Garrido Salas; Eduardo I. Boemo (IEEE Des. Test Comput., 2000)

Run-Time Reconfiguration to Check Temperature in Custom Computers: An Application of JBits Technology. - Sergio López-Buedo; Paula Riviere; Pablo Pernas; Eduardo I. Boemo (FPL, 2002)

FSM Decomposition for Low Power in FPGA. - Gustavo Sutter; Elias Todorovich; Sergio López-Buedo; Eduardo I. Boemo (FPL, 2002)

A Tool for Activity Estimation in FPGAs. - Elias Todorovich; M. Gilabert; Gustavo Sutter; Sergio López-Buedo; Eduardo I. Boemo (FPL, 2002)

Low-Power FSMs in FPGA: Encoding Alternatives. - Gustavo Sutter; Elias Todorovich; Sergio López-Buedo; Eduardo I. Boemo (PATMOS, 2002)

Using Partial Reconfiguration in Cryptographic Applications: An Implementation of the IDEA Algorithm. - Iván González 004; Sergio López-Buedo; Francisco J. Gómez; Javier Martínez (FPL, 2003)

Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report. - Sergio López-Buedo; Eduardo I. Boemo (FPGA, 2004)

Hardware-Accelerated SSH on Self-Reconfigurable Systems. - Iván González 004; Francisco J. Gomez-Arribas; Sergio López-Buedo (FPT, 2005)

Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. - Chun Hok Ho; Philip Heng Wai Leong; Wayne Luk; Steven J. E. Wilton; Sergio López-Buedo (FCCM, 2006)

A Quality of Service Assessment Technique for Large-Scale Management of Multimedia Flows. - José Luis García-Dorado; Javier Aracil 001; José Alberto Hernández 001; Sergio López-Buedo; Jorge E. López de Vergara; Pedro Reviriego; Gabriel Huecas; Santiago Pavón; Juan Quemada (MMNS, 2007)

Self-Reconfigurable Embedded Systems on Low-Cost FPGAs. - Iván González 004; Estanislao Aguayo; Sergio López-Buedo (IEEE Micro, 2007)

A Framework to Improve IP Portability on Reconfigurable Computers. - Miaoqing Huang; Iván González 004; Sergio López-Buedo; Tarek A. El-Ghazawi (ERSA, 2008)

Implementation of secure applications in self-reconfigurable systems. - Iván González 004; Sergio López-Buedo; Francisco J. Gomez-Arribas (Microprocess. Microsystems, 2008)

Portable library development for reconfigurable computing systems: A case study. - Proshanta Saha; Esam El-Araby; Miaoqing Huang; Mohamed Taher; Sergio López-Buedo; Tarek A. El-Ghazawi; Chang Shu 003; Kris Gaj; Alan Michalski; Duncan A. Buell (Parallel Comput., 2008)

High-accuracy network monitoring using ETOMIC testbed. - Victor Moreno; Jaime J. Garnica; Francisco J. Gomez-Arribas; Sergio López-Buedo; Iván González 004; Javier Aracil 001; Mikel Izal; Eduardo Magaña; Daniel Morató (NGI, 2011)

Characterization of the busy-hour traffic of IP networks based on their intrinsic features. - José Luis García-Dorado; José Alberto Hernández 001; Javier Aracil 001; Jorge E. López de Vergara; Sergio López-Buedo (Comput. Networks, 2011)

High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations. - Diego Sanchez-Roman; Gustavo Sutter; Sergio López-Buedo; Iván González 004; Francisco J. Gomez-Arribas; Javier Aracil 001; Francisco Palacios (IEEE Des. Test Comput., 2011)

A FPGA-based scalable architecture for URL legal filtering in 100GbE networks. - Jaime J. Garnica; Sergio López-Buedo; Víctor López 004; Javier Aracil 001; José María Gómez Hidalgo (ReConFig, 2012)

A Convolve-And-MErge Approach for Exact Computations on High-Performance Reconfigurable Computers. - Esam El-Araby; Iván González 004; Sergio López-Buedo; Tarek A. El-Ghazawi (Int. J. Reconfigurable Comput., 2012)

Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture. - Iván González 004; Sergio López-Buedo; Gustavo Sutter; Diego Sanchez-Roman; Francisco J. Gomez-Arribas; Javier Aracil 001 (J. Syst. Archit., 2012)

IDEALIST control and service management solutions for dynamic and adaptive flexi-grid DWDM networks. - Raul Muñoz 001; Víctor López 001; Ramon Casellas; Óscar González de Dios; Filippo Cugini; Nicola Sambo; Antonio D'Errico; Ori Gerstel; Daniel King; Sergio López-Buedo; Patricia Layec; Antonio Cimmino; et al. (Future Network & Mobile Summit, 2013)

Accurate and flexible flow-based monitoring for high-speed networks. - Marco Forconesi; Gustavo Sutter; Sergio López-Buedo; Javier Aracil 001 (FPL, 2013)

FPGA acceleration using high-level languages of a Monte-Carlo method for pricing complex options. - Diego Sanchez-Roman; Victor Moreno; Sergio López-Buedo; Gustavo Sutter; Iván González 004; Francisco J. Gomez-Arribas; Javier Aracil 001 (J. Syst. Archit., 2013)

TNT10G: A high-accuracy 10 GbE traffic player and recorder for multi-Terabyte traces. - Jose Fernando Zazo; Marco Forconesi; Sergio López-Buedo; Gustavo Sutter; Javier Aracil 001 (ReConFig, 2014)

Bridging the gap between hardware and software open source network developments. - Marco Forconesi; Gustavo Sutter; Sergio López-Buedo; Jorge E. López de Vergara; Javier Aracil 001 (IEEE Netw., 2014)

Leveraging open source platforms and high-level synthesis for the design of FPGA-based 10 GbE active network probes. - Mario Ruiz; Gustavo Sutter; Sergio López-Buedo; Javier Ramos 002; Jorge E. López de Vergara; Javier Aracil 001 (ReConFig, 2015)

A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances. - Jose Fernando Zazo; Sergio López-Buedo; Yury Audzevich; Andrew W. Moore 002 (ReConFig, 2015)

Rack-scale disaggregated cloud data centers: The dReDBox project vision. - Kostas Katrinis; Dimitris Syrivelis; Dionisios N. Pnevmatikatos; Georgios Zervas; Dimitris Theodoropoulos; Iordanis Koutsopoulos; K. Hasharoni; Daniel Raho; Christian Pinto; Felix Espina; Sergio López-Buedo; Qianqiao Chen; et al. (DATE, 2016)

On interconnecting and orchestrating components in disaggregated data centers: The dReDBox project vision. - Kostas Katrinis; Georgios Zervas; Dionisios N. Pnevmatikatos; Dimitris Syrivelis; Theoni Alexoudi; Dimitris Theodoropoulos; Daniel Raho; Christian Pinto; Felix Espina; Sergio López-Buedo; Qianqiao Chen; Mario Nemirovsky; et al. (EuCNC, 2016)

Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. - Mario Ruiz; Javier Ramos 002; Gustavo Sutter; Sergio López-Buedo; Jorge E. López de Vergara; C. Sisterna (FPL, 2016)

FPGA-based encrypted network traffic identification at 100 Gbit/s. - Mario Ruiz; Gustavo Sutter; Sergio López-Buedo; Jorge E. López de Vergara (ReConFig, 2016)

Automated synthesis of FPGA-based packet filters for 100 Gbps network monitoring applications. - Jose Fernando Zazo; Sergio López-Buedo; Gustavo Sutter; Javier Aracil 001 (ReConFig, 2016)

Accurate and affordable packet-train testing systems for multi-gigabit-per-second networks. - Mario Ruiz; Javier Ramos 002; Gustavo Sutter; Jorge E. López de Vergara; Sergio López-Buedo; Javier Aracil 001 (IEEE Commun. Mag., 2016)

Diluting the Scalability Boundaries: Exploring the Use of Disaggregated Architectures for High-Level Network Data Analysis. - Carlos Vega; Jose Fernando Zazo; Hugo Meyer; Ferad Zyulkyarov; Sergio López-Buedo; Javier Aracil 001 (HPCC/SmartCity/DSS, 2017)

An FPGA-based approach for packet deduplication in 100 gigabit-per-second networks. - Mario Ruiz; Gustavo Sutter; Sergio López-Buedo; Jose Fernando Zazo; Jorge E. López de Vergara (ReConFig, 2017)

A single-FPGA architecture for detecting heavy hitters in 100 Gbit/s ethernet links. - Jose Fernando Zazo; Sergio López-Buedo; Mario Ruiz; Gustavo Sutter (ReConFig, 2017)

dReDBox: Materializing a full-stack rack-scale system prototype of a next-generation disaggregated datacenter. - Maciej Bielski; Ilias Syrigos; Kostas Katrinis; Dimitris Syrivelis; Andrea Reale; Dimitris Theodoropoulos; Nikolaos Alachiotis 001; Dionisis N. Pnevmatikatos; E. H. Pap; George Zervas; Vaibhawa Mishra; Arsalan Saljoghei; et al. (DATE, 2018)

FPGA-based TCP/IP Checksum Offloading Engine for 100 Gbps Networks. - Gustavo Sutter; Mario Ruiz; Sergio López-Buedo; Gustavo Alonso (ReConFig, 2018)

Understanding PCIe performance for end host networking. - Rolf Neugebauer; Gianni Antichi; José Fernando Zazo; Yury Audzevich; Sergio López-Buedo; Andrew W. Moore 002 (SIGCOMM, 2018)

Limago: An FPGA-Based Open-Source 100 GbE TCP/IP Stack. - Mario Ruiz; David Sidler; Gustavo Sutter; Gustavo Alonso; Sergio López-Buedo (FPL, 2019)

A Latency-Aware Real-Time Video Surveillance Demo: Network Slicing for Improving Public Safety. - Behnam Shariati; Jose-Juan Pedreno-Manresa; Annika Dochhan; Abubakar Siddique Muqaddas; Ramon Casellas; Óscar González de Dios; Lourdes Luque Canto; Bodo Lent; Jorge E. López de Vergara; Sergio López-Buedo; Francisco Javier Moreno; Pablo Pavón 001; et al. (OFC, 2021)

Demonstration of latency-aware 5G network slicing on optical metro networks. - Behnam Shariati; Luis Velasco 001; Jose-Juan Pedreno-Manresa; Annika Dochhan; Ramon Casellas; Abubakar Siddique Muqaddas; Óscar González de Dios; Lourdes Luque Canto; Bodo Lent; Jorge E. López de Vergara; Sergio López-Buedo; Francisco Javier Moreno; et al. (CoRR, 2022)

Demonstration of latency-aware 5G network slicing on optical metro networks. - Behnam Shariati; Luis Velasco 001; Jose-Juan Pedreno-Manresa; Annika Dochhan; Ramon Casellas; Abubakar Siddique Muqaddas; Óscar González de Dios; Lourdes Luque Canto; Bodo Lent; Jorge E. López de Vergara; Sergio López-Buedo; Francisco-Javier Moreno-Muro; et al. (JOCN, 2022)

Enhancing Conditional Stalling to Boost Performance of Stream-Processing Logic With RAW Dependencies. - Tobias Alonso; Gustavo Sutter; Sergio López-Buedo; Jorge E. López de Vergara (IEEE Trans. Circuits Syst. II Express Briefs, 2023)