Knowledge-intensive, causal reasoning for analog circuit topology synthesis in emergent and innovative applications. - Fanshu Jiao; Sergio Montano; Alex Doboli (DATE, 2015)

Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies. - Fanshu Jiao; Sergio Montano; Cristian Ferent; Alex Doboli; Simona Doboli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A Generated Multirate Signal Analysis RISC-V SoC in 16nm FinFET. - Stevo Bailey; Jaeduk Han; Paul Rigge; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (A-SSCC, 2018)

A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. - Steven Bailey; Paul Rigge; Jaeduk Han; Richard Lin; Eric Chang; Howard Mao; Zhongkai Wang; Chick Markley; Adam M. Izraelevitz; Angie Wang; Nathan Narevsky; Woo-Rham Bae; et al. (IEEE J. Solid State Circuits, 2019)

A RISC-V Neuromorphic Micro-Controller Unit (vMCU) with Event-Based Physical Interface and Computational Memory for Low-Latency Machine Perception and Intelligence at the Edge. - Daniel R. Mendat; Jonah P. Sengupta; Gaspar Tognetti; Martin Villemur; Philippe O. Pouliquen; Sergio Montano; Kayode Sanni; Jamal Lottier Molin; Nishant Zachariah; Isidoros Doxas; Andreas G. Andreou (ISCAS, 2023)