Architectural Requirements for Energy Efficient Execution of Graph Analytics Applications. - Muhammet Mustafa Ozdal; Serif Yesil; Taemin Kim; Andrey Ayupov; Steven M. Burns; Ozcan Ozturk 001 (ICCAD, 2015)

Hardware Accelerator Design for Data Centers. - Serif Yesil; Muhammet Mustafa Ozdal; Taemin Kim; Andrey Ayupov; Steven M. Burns; Ozcan Ozturk 001 (ICCAD, 2015)

FPGA implementation of a fault-tolerant application-specific NoC design. - Serif Yesil; Suleyman Tosun; Özcan Özturk 001 (DTIS, 2016)

Energy Efficient Architecture for Graph Analytics Accelerators. - Muhammet Mustafa Ozdal; Serif Yesil; Taemin Kim; Andrey Ayupov; John Greth; Steven M. Burns; Özcan Özturk 001 (ISCA, 2016)

On Dynamic Precision Scaling. - Serif Yesil; Ismail Akturk; Ulya R. Karpuzcu (CoRR, 2017)

Graph Analytics Accelerators for Cognitive Systems. - Muhammet Mustafa Ozdal; Serif Yesil; Taemin Kim; Andrey Ayupov; John Greth; Steven M. Burns; Ozcan Ozturk 001 (IEEE Micro, 2017)

Toward Dynamic Precision Scaling. - Serif Yesil; Ismail Akturk; Ulya R. Karpuzcu (IEEE Micro, 2018)

A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators. - Andrey Ayupov; Serif Yesil; Muhammet Mustafa Ozdal; Taemin Kim; Steven M. Burns; Ozcan Ozturk 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Understanding priority-based scheduling of graph algorithms on a shared-memory platform. - Serif Yesil; Azin Heidarshenas; Adam Morrison 001; Josep Torrellas (SC, 2019)

Snug: architectural support for relaxed concurrent priority queueing in chip multiprocessors. - Azin Heidarshenas; Tanmay Gangwani; Serif Yesil; Adam Morrison 001; Josep Torrellas (ICS, 2020)

V-Combiner: speeding-up iterative graph processing on a shared-memory platform with vertex merging. - Azin Heidarshenas; Serif Yesil; Dimitrios Skarlatos 002; Sasa Misailovic; Adam Morrison 001; Josep Torrellas (ICS, 2020)

Speeding up SpMV for power-law graph analytics by enhancing locality & vectorization. - Serif Yesil; Azin Heidarshenas; Adam Morrison 001; Josep Torrellas (SC, 2020)

Dense dynamic blocks: optimizing SpMM for processors with vector and matrix units using machine learning techniques. - Serif Yesil; José E. Moreira; Josep Torrellas (ICS, 2022)

Scheduling for heterogeneous systems in accelerator-rich environments. - Serif Yesil; Ozcan Ozturk 001 (J. Supercomput., 2022)

SPADE: A Flexible and Scalable Accelerator for SpMM and SDDMM. - Gerasimos Gerogiannis; Serif Yesil; Damitha Lenadora; Dingyuan Cao 002; Charith Mendis; Josep Torrellas (ISCA, 2023)

WISE: Predicting the Performance of Sparse Matrix Vector Multiplication with Machine Learning. - Serif Yesil; Azin Heidarshenas; Adam Morrison 001; Josep Torrellas (PPoPP, 2023)

Input-sensitive dense-sparse primitive compositions for GNN acceleration. - Damitha Lenadora; Vimarsh Sathia; Gerasimos Gerogiannis; Serif Yesil; Josep Torrellas; Charith Mendis (CoRR, 2023)

Efficient parallel implementation of the multiplicative weight update method for graph-based linear programs. - Caleb Ju; Serif Yesil; Mengyuan Sun; Chandra Chekuri; Edgar Solomonik (CoRR, 2023)

Analysis of Parallel Graph Applications. - Funda Atik; Serif Yesil; Hamza Ouarnoughi; Smaïl Niar; Ozcan Ozturk 001 (ICPADS, 2024)