A 5-Gbps 1.7 pJ/bit ditherless CDR with optimal phase interval detection. - Myeong-Jae Park; Hanseok Kim; Seuk Son; Jaeha Kim (CICC, 2012)

Design of low-power high-radix switch fabric with partially-activated input and output lines. - Jihyun Ryoo; Seuk Son; Jaeha Kim (ISOCC, 2012)

A 2.3-mW, 5-Gb/s Low-Power Decision-Feedback Equalizer Receiver Front-End and its Two-Step, Minimum Bit-Error-Rate Adaptation Algorithm. - Seuk Son; Hanseok Kim; Myeong-Jae Park; Kyung-Hoon Kim; E-Hung Chen; Brian S. Leibowitz; Jaeha Kim (IEEE J. Solid State Circuits, 2013)

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function. - Sigang Ryu; Hwanseok Yeo; Yoontaek Lee; Seuk Son; Jaeha Kim (IEEE J. Solid State Circuits, 2014)

13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications. - Hwanseok Yeo; Sigang Ryu; Yoontaek Lee; Seuk Son; Jaeha Kim (ISSCC, 2016)

A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery. - Seuk Son; Sigang Ryu; Hwanseok Yeo; Jaeha Kim (IEEE J. Solid State Circuits, 2019)

An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops. - Sigang Ryu; Seuk Son; Jaeha Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC. - Sigang Ryu; Chan Young Park; Wooryeol Kim; Seuk Son; Jaeha Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)