FinFET based SRAM bitcell design for 32 nm node and below. - Seung Chul Song; M. Abu-Rahma; Geoffrey Yeap (Microelectron. J., 2011)

Improved device variability in scaled MOSFETs with deeply retrograde channel profile. - Jason Woo; Po-Yen Chien; Frank Yang; Seung Chul Song; P. R. Chidi Chidambaram; Joseph Wang 002; Geoffrey Yeap (Microelectron. Reliab., 2014)

Transistor-interconnect mobile system-on-chip co-design method for holistic battery energy minimization. - N. N. Mojumder; Seung Chul Song; K. Rim; J. Xu; Joseph Wang; J. Zhu; Milena Vratonjic; K. Lin; Martin Saint-Laurent; Paul Bassett; Geoffrey Yeap (VLSIC, 2015)

Holistic technology optimization and key enablers for 7nm mobile SoC. - Seung Chul Song; J. Xu; N. N. Mojumder; K. Rim; D. Yang; Jerry Bao; J. Zhu; Joseph Wang; Mustafa Badaroglu; V. Machkaoutsan; Praneeth Narayanasetti; B. Bucki; et al. (VLSIC, 2015)

SRAM Design for 22-nm ETSOI Technology: Selective Cell Current Boosting and Asymmetric Back-Gate Write-Assist Circuit. - Younghwi Yang; Juhyun Park; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Single-Ended 9T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Read Performance in 22-nm FinFET Technology. - Younghwi Yang; Juhyun Park; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Unified Technology Optimization Platform using Integrated Analysis (UTOPIA) for holistic technology, design and system co-optimization at <= 7nm nodes. - Seung Chul Song; J. Xu; D. Yang; K. Rim; P. Feng; Jerry Bao; J. Zhu; Joseph Wang; G. Nallapati; Mustafa Badaroglu; Praneeth Narayanasetti; B. Bucki; et al. (VLSI Circuits, 2016)

Single Bit-Line 7T SRAM Cell for Near-Threshold Voltage Operation With Enhanced Performance and Energy in 14 nm FinFET Technology. - Younghwi Yang; Hanwool Jeong; Seung Chul Song; Joseph Wang; Geoffrey Yeap; Seong-Ook Jung (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

PPAC scaling enablement for 5nm mobile SoC technology. - Mustafa Badaroglu; Jeff Xu; John Zhu; Da Yang 007; Jerry Bao; Seung Chul Song; Peijie Feng; Romain Ritzenthaler; Hans Mertens; Geert Eneman; Naoto Horiguchi; Jeffrey Smith 003; et al. (ESSDERC, 2017)

Sense-Amplifier-Based Flip-Flop With Transition Completion Detection for Low-Voltage Operation. - Hanwool Jeong; Tae Woo Oh; Seung Chul Song; Seong-Ook Jung (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Self-Timed Pulsed Latch for Low-Voltage Operation With Reduced Hold Time. - Hanwool Jeong; Juhyun Park; Seung Chul Song; Seong-Ook Jung (IEEE J. Solid State Circuits, 2019)