On-Chip Cache Memory Resilience. - Seung H. Hwang; Gwan S. Choi (HASE, 1998)

Selective-set-invalidation (SSI) for soft-error-resilient cache architecture. - Seung H. Hwang; Gwan S. Choi (SIGARCH Comput. Archit. News, 1999)

A Reliability Testing Environment for Off-the-Shelf Memory Subsystems. - Seung H. Hwang; Gwan S. Choi (IEEE Des. Test Comput., 2000)