A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. - Young-Soo Sohn; Seung-Jun Bae; Hong-June Park; Changhyun Kim; Soo-In Cho (CICC, 2003)

A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme. - Seung-Jun Bae; Hyung-Joon Chi; Young-Soo Sohn; Hong-June Park (IEEE J. Solid State Circuits, 2005)

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques. - Seung-Jun Bae; Young-Soo Sohn; Kwang-Il Park; Kyoung-Ho Kim; Dae-Hyun Chung; Jingook Kim; Si-Hong Kim; Min-Sang Park; Jae-Hyung Lee; Sam-Young Bang; Ho-Kyung Lee; In-Soo Park; et al. (ISSCC, 2008)

A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration. - Hyung-Joon Chi; Jae-Seung Lee; Seong-Hwan Jeon; Seung-Jun Bae; Jae-Yoon Sim; Hong-June Park (ISSCC, 2008)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (ISSCC, 2009)

A 0.13-µm CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN. - Kyung-Soo Ha; Lee-Sup Kim; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Kinam Kim (IEEE J. Solid State Circuits, 2009)

A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling. - Seung-Jun Bae; Hyung-Joon Chi; Young-Soo Sohn; Jae-Seung Lee; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. - Jun-Hyun Bae; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Joo-Sun Choi; Young-Hyun Jun; Jae-Yoon Sim; Hong-June Park (CICC, 2010)

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (ISSCC, 2010)

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW. - Seung-Jun Bae; Young-Soo Sohn; Tae-Young Oh; Si-Hong Kim; Yun-Seok Yang; Dae-Hyun Kim 003; Sang-Hyup Kwak; Ho-Seok Seol; Chang-Ho Shin; Min-Sang Park; Gong-Heom Han; Byeong-Cheol Kim; et al. (ISSCC, 2011)

Performance of greedy policies for downlink scheduling in networks with relay stations. - Seung-Jun Bae; JaeSheung Shin (IEICE Electron. Express, 2011)

A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. - Hyung-Joon Chi; Jae-Seung Lee; Seong-Hwan Jeon; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2011)

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction. - Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Min-Sang Park; Ji-Hoon Lim; Yong-Ki Cho; Dae-Hyun Kim 003; Dong-Min Kim; Hye-Ran Kim; Hyun-Joong Kim; Jin-Hyun Kim; Jin-Kook Kim; et al. (IEEE J. Solid State Circuits, 2011)

An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. - Il-Min Yi; Seung-Jun Bae; Young-Soo Sohn; Jae-Yoon Sim; Hong-June Park (ISOCC, 2012)

An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. - Young-Sik Kim; Seon-Kyoo Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Bae Lee; Joo-Sun Choi; Hong-June Park; Jae-Yoon Sim (ISSCC, 2012)

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. - Ji-Hwan Seol; Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Joo-Sun Choi; Lee-Sup Kim (ISSCC, 2013)

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation. - Tae-Young Oh; Hoeju Chung; Young-Chul Cho; Jang-Woo Ryu; Kiwon Lee; Changyoung Lee; Jin-Il Lee; Hyoung-Joo Kim 002; Min-Soo Jang; Gong-Heum Han; Kihan Kim; Daesik Moon; et al. (ISSCC, 2014)

A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. - Sang-Hye Chung; Young-Ju Kim 001; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. - Chang-Kyo Lee; Min-Su Ahn; Daesik Moon; Kiho Kim; Yoon-Joo Eom; Won-Young Lee; Jongmin Kim; Sanghyuk Yoon; Baekkyu Choi; Seokhong Kwon; Joon-Young Park; Seung-Jun Bae; et al. (VLSIC, 2015)

A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. - Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

Crosstalk avoidance code for direct pass-through architecture. - Minhye Kim; Soochang Chae; Young-Ju Kim 001; Seung-Jun Bae; Lee-Sup Kim (ISCAS, 2016)

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. - Hye-Yoon Joo; Seung-Jun Bae; Young-Soo Sohn; Young-Sik Kim; Kyung-Soo Ha; Min-Su Ahn; Young-Ju Kim 001; Yong-Jun Kim; Ju-Hwan Kim; Won-Jun Choi; Chang-Ho Shin; Soo Hwan Kim; et al. (ISSCC, 2016)

A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. - Il-Min Yi; Seung-Jun Bae; Min-Kyun Chae; Soo-Min Lee; Young Jae Jang; Young-Chul Cho; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (VLSI Circuits, 2016)

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. - Il-Min Yi; Soo-Min Lee; Seung-Jun Bae; Young-Soo Sohn; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Gil-Hoon Cha; Jin-Hyeok Baek; Daesik Moon; Yoon-Joo Eom; Tae-Sung Kim; Hyunyoon Cho; Young Hoon Son; Seonghwan Kim 002; et al. (A-SSCC, 2017)

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. - Yohan Frans; Ichiro Fujimori; Seung-Jun Bae; Samuel Palermo; Hideyuki Nosaka; Simone Erba (ISSCC, 2017)

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices. - Hye-Jung Kwon; Eunsung Seo; ChangYong Lee; Young-Hun Seo; Gong-Heum Han; Hye-Ran Kim; Jong-Ho Lee; Min-Su Jang; Sung-Geun Do; Seung-Hyun Cho; Jae-Koo Park; Su-Yeon Doo; et al. (ISSCC, 2017)

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme. - Chang-Kyo Lee; Yoon-Joo Eom; Jin-Hee Park; Junha Lee; Hye-Ran Kim; Kihan Kim; Young Choi; Ho-Jun Chang; Jonghyuk Kim; Jong-Min Bang; Seungjun Shin; Hanna Park; et al. (ISSCC, 2017)

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (ISSCC, 2017)

Session 23 overview: DRAM, MRAM & DRAM interfaces. - Takefumi Yoshikawa; Seung-Jun Bae; Leland Chang (ISSCC, 2017)

Session 12 overview: DRAM: Memory subcommittee. - Seung-Jun Bae; Wolfgang Spirkl; Leland Chang (ISSCC, 2018)

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Yoon-Joo Eom; Young-Sik Kim; Min-Su Ahn; Yong-Hun Kim; Sang-Hoon Jung; Sung-Geun Do; Chang-Yong Lee; Jae-Sung Kim; Dong-Seok Kang; et al. (ISSCC, 2018)

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. - Jin-Hyeok Baek; Chang-Kyo Lee; Kiho Kim; Daesik Moon; Gil-Hoon Cha; Jin-Seok Heo; Min-Su Ahn; Dong-Ju Kim; Jae-Joon Song; Seokhong Kwon; Jongmin Kim; Kyung-Soo Kim; et al. (VLSI Circuits, 2018)

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM. - Chang-Kyo Lee; Junha Lee; Kiho Kim; Jin-Seok Heo; Jin-Hyeok Baek; Gil-Hoon Cha; Daesik Moon; Dong-Hun Lee; Jong-Wook Park; Seunseob Lee; Si-Hyeong Cho; Young-Ryeol Choi; et al. (IEEE J. Solid State Circuits, 2018)

A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. - Il-Min Yi; Min-Kyun Chae; Seok-Hun Hyun; Seung-Jun Bae; Jung-Hwan Choi; Seong-Jin Jang; Byungsub Kim; Jae-Yoon Sim; Hong-June Park (IEEE J. Solid State Circuits, 2018)

An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS. - Xi Yang; Seung-Jun Bae; Hae-Seung Lee (ESSCIRC, 2019)

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration. - Jin-Seok Heo; Kihan Kim; Dong-Hoon Lee; Chang-Kyo Lee; Daesik Moon; Kiho Kim; Jin-Hyeok Baek; Sung-Woo Yoon; Hui-Kap Yang; Kyungryun Kim; Youngjae Kim; Bokgue Park; et al. (VLSI Circuits, 2019)

Introduction to the Special Issue on the 2018 International Solid-State Circuits Conference (ISSCC). - Yohan Frans; Wim Dehaene; Masato Motomura; Seung-Jun Bae (IEEE J. Solid State Circuits, 2019)

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. - Young-Ju Kim 001; Hye-Jung Kwon; Su-Yeon Doo; Min-Su Ahn; Yong-Hun Kim; Yong Jae Lee; Dong-Seok Kang; Sung-Geun Do; Chang-Yong Lee; Gun-hee Cho; Jae-Koo Park; Jae-Sung Kim; et al. (IEEE J. Solid State Circuits, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques. - Kyung-Soo Ha; Seungseob Lee; Youn-Sik Park; Hyuck-Joon Kwon; Tae-Young Oh; Young-Soo Sohn; Seung-Jun Bae; Kwang-Il Park; Jung-Bae Lee; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; et al. (IEEE J. Solid State Circuits, 2020)

Session 16 Overview: Computation in Memory Memory Subcommittee. - Meng-Fan Chang; Ru Huang 001; Seung-Jun Bae (ISSCC, 2021)

25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. - Yong-Hun Kim; Hyung-Jin Kim; Jaemin Choi; Min-Su Ahn; Dongkeon Lee; Seung-Hyun Cho; Dong-Yeon Park; Young-Jae Park; Min-Soo Jang; Yong-Jun Kim; Jinyong Choi; Sung-Woo Yoon; et al. (ISSCC, 2021)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)

A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface. - Min-Kyun Chae; Hye-Jung Kwon; Seung-Jun Bae; Nam-Jong Kim; Hong-June Park (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Donghun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (A-SSCC, 2023)

A 1.06V 5Gb/s/pin 16Gb LPDDR4x DRAM Adopting Sense Amplifier with AC-Coupled Equalizer, Stacked Output Driver, and Clock MUX with Inverter-Based Transmission Gate for Mobile and Automotive Application. - Young-Gil Go; Hyun-A. Ahn; Yoo-Chang Sung; Myung-Hun Jung; Ji-Geon Yeom; Hun-Dae Choi; Janghoo Kim; Hyunjin Ko; Miyoung Woo; Seong-O. Huh; Seung-Jun Bae; Tae-Young Oh (A-SSCC, 2024)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications. - Hyun-A. Ahn; Yoo-Chang Sung; Yong-Hun Kim; Janghoo Kim; Kihan Kim; Dong-Hun Lee; Young-Gil Go; Jae-Woo Lee; Jae-Woo Jung; Yong-Hyun Kim; Garam Choi; Jun-Seo Park; et al. (IEEE J. Solid State Circuits, 2024)

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process. - Jin-Hyeok Baek; Jang-Hoo Kim; Yoo-Chang Sung; Jae-Woo Jeong; Jin-Kwan Park; Hyun-Kyu Oh; Bo-Hyeon Lee; Dong-Wan Ko; Tae-Seob Oh; Seung-Gi Hong; Chang-Ki Kwon; Daihyun Lim; et al. (ISSCC, 2025)

Learning High-Quality Latent Representations for Anomaly Detection and Signal Integrity Enhancement in High-Speed Signals. - Muhammad Usama; Hee-Deok Jang; Soham Shanbhag; Yoo-Chang Sung; Seung-Jun Bae; Dong Eui Chang (CoRR, 2025)