A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)

A 192-Gb 12-High 896-GB/s HBM3 DRAM With a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Jinhyung Lee; Kyungjun Cho; Ji Hwan Park; Junil Moon; Sung-Hak Lee; Tae-Kyun Kim 001; Sanghoon Oh; Seokwoo Choi; Yongsuk Choi; Ho Sung Cho; Tae-Sik Yun; et al. (IEEE J. Solid State Circuits, 2023)

13.4 A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization. - Jinhyung Lee; Kyungjun Cho; Chang Kwon Lee; Yeonho Lee 002; Jae-Hyung Park; Su-Hyun Oh; Yucheon Ju; Chunseok Jeong; Ho Sung Cho; Jaeseung Lee; Tae-Sik Yun; Jin Hee Cho; et al. (ISSCC, 2024)