Variable VCC design techniques for battery-operated DRAMs. - Seung-Moon Yoo; Ejaz Haq; Seung-Hoon Lee; Yun-Ho Choi; Soo-In Cho; Nam-Soo Kang; Daeje Chin (IEEE J. Solid State Circuits, 1993)

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

Low-voltage, high-speed circuit designs for gigabit DRAMs. - Kyu-Chan Lee; Changhyun Kim; Dong-Ryul Ryu; Jai-Hoon Sim; Sang-Bo Lee; Byung-Sik Moon; Keum-Yong Kim; Nam-Jong Kim; Seung-Moon Yoo; Hongil Yoon; Jei-Hwan Yoo; Soo-In Cho (IEEE J. Solid State Circuits, 1997)

A Bootstrapped NMOS Charge Recovery Logic. - Seung-Moon Yoo; Seung-Moon Kang (Great Lakes Symposium on VLSI, 1998)

NMOS Energy Recovery Logic. - Chulwoo Kim; Seung-Moon Yoo; Sung-Mo Kang (Great Lakes Symposium on VLSI, 1999)

No-Race Charge-Recycling Differential Logic (NCDL). - Seung-Moon Yoo; Sung-Mo Kang (Great Lakes Symposium on VLSI, 1999)

FlexRAM: Toward an Advanced Intelligent Memory System. - Yi Kang; Wei Huang; Seung-Moon Yoo; Diana Keen; Zhenzhou Ge; Vinh Vi Lam; Josep Torrellas; Pratap Pattnaik (ICCD, 1999)

CMOS Pass-gate No-race Charge-recycling Logic (CPNCL). - Seung-Moon Yoo; Sung-Mo Kang (ISCAS (1), 1999)

Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (Intelligent Memory Systems, 2000)

New high performance sub-1 V circuit technique with reduced standby current and robust data holding. - Seung-Moon Yoo; Sung-Mo Kang (ISCAS, 2000)

A framework for dynamic energy efficiency and temperature management. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (MICRO, 2000)

Effective algorithms for cache-level compression. - Edward Ahn; Seung-Moon Yoo; Sung-Mo Kang (ACM Great Lakes Symposium on VLSI, 2001)

2-level LFSR scheme with asynchronous test pattern transfer for low cost and high efficiency build-in-self-test. - Seung-Moon Yoo; Seong-Ook Jung; Sung-Mo Kang (ACM Great Lakes Symposium on VLSI, 2001)

Skew-tolerant high-speed (STHS) domino logic. - Seong-Ook Jung; Seung-Moon Yoo; Ki-Wook Kim; Sung-Mo Kang (ISCAS (4), 2001)

Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. - Seung-Moon Yoo; Seong-Ook Jung; Sung-Mo Kang (ISCAS (4), 2001)

New current-mode sense amplifiers for high density DRAM and PIM architectures. - Seung-Moon Yoo; Chulwoo Kim; Seong-Ook Jung; Kwang-Hyun Baek; Sung-Mo Kang (ISCAS (4), 2001)

L1 data cache decomposition for energy efficiency. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (ISLPED, 2001)

The Design of DEETM: a Framework for Dynamic Energy Efficiency and Temperature Management. - Michael C. Huang 001; Jose Renau; Seung-Moon Yoo; Josep Torrellas (J. Instr. Level Parallelism, 2001)

Design of Energy Efficient SOC With PIM Architecture and Deep Submicron Circuit Techniques - Seung-Moon Yoo (2001)

A semi-custom voltage-island technique and its application to high-speed serial links. - Juan Antonio Carballo; Jeffrey L. Burns; Seung-Moon Yoo; Ivan Vo; V. Robert Norman (ISLPED, 2003)

Requirement-based design methods for adaptive communications links. - Juan Antonio Carballo; Kevin J. Nowka; Seung-Moon Yoo; Ivan Vo; Clay Cranford; V. Robert Norman (DAC, 2004)