A 14-b linear capacitor self-trimming pipelined ADC. - Seung-Tak Ryu; Sourja Ray; Bang-Sup Song; Gyu-Hyeong Cho; Kantilal Bacrania (IEEE J. Solid State Circuits, 2004)

A 10b 50MS/s pipelined ADC with opamp current reuse. - Seung-Tak Ryu; Bang-Sup Song; Kantilal Bacrania (ISSCC, 2006)

A 10-bit 50-MS/s Pipelined ADC With Opamp Current Reuse. - Seung-Tak Ryu; Bang-Sup Song; Kantilal Bacrania (IEEE J. Solid State Circuits, 2007)

A Time-interleaved Flash-SAR Architecture for High Speed A/D Conversion. - Ba Sung; Sang-Hyun Cho; Chang-Kyo Lee; Jong-In Kim; Seung-Tak Ryu (ISCAS, 2009)

A Fully On-Chip Gm-Opamp-RC Based Preamplifier for Electret Condenser Microphones. - Huy-Binh Le; Seung-Tak Ryu; Sang-Gug Lee 001 (IEICE Trans. Electron., 2009)

A 550µW 10b 40MS/s SAR ADC with multistep addition-only digital error correction. - Sang-Hyun Cho; Chang-Kyo Lee; Jong-Kee Kwon; Seung-Tak Ryu (CICC, 2010)

A novel readout IC with high noise immunity for charge-based touch screen panels. - Junhyeok Yang; Seungchul Jung; Young-Jin Woo; Jinyong Jeon; Sungwoo Lee; Changbyung Park; Hyunsik Kim; Seung-Tak Ryu; Gyu-Hyeong Cho (CICC, 2010)

Yield-Ensuring DAC-Embedded Opamp Design Based on Accurate Behavioral Model Development. - Yeong-Shin Jang; Hoai-Nam Nguyen; Seung-Tak Ryu; Sang-Gug Lee 001 (IEICE Trans. Electron., 2010)

A time-domain latch interpolation technique for low power flash ADCs. - Jong-In Kim; Wan Kim; Barosaim Sung; Seung-Tak Ryu (CICC, 2011)

A 0.014mm2 9b switched-current DAC for AMOLED mobile display drivers. - Hyunsik Kim; Jinyong Jeon; Sungwoo Lee; Junhyeok Yang; Seung-Tak Ryu; Gyu-Hyeong Cho (ISSCC, 2011)

A 550-μW 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction. - Sang-Hyun Cho; Chang-Kyo Lee; Jong-Kee Kwon; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2011)

A Compact-Sized 9-Bit Switched-Current DAC for AMOLED Mobile Display Drivers. - Hyunsik Kim; Jinyong Jeon; Sungwoo Lee; Junhyeok Yang; Seung-Tak Ryu; Gyu-Hyeong Cho (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Long Reset-Time Power-On Reset Circuit With Brown-Out Detection Capability. - Huy-Binh Le; Xuan-Dien Do; Sang-Gug Lee 001; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control. - Hyeok-Ki Hong; Wan Kim; Sun-Jae Park; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (CICC, 2012)

A 40mV transformer-reuse self-startup boost converter with MPPT control for thermoelectric energy harvesting. - Jong-Pil Im; Se-Won Wang; Kang-Ho Lee; Young-Jin Woo; Young-sub Yuk; Tae-Hwang Kong; Sung-Wan Hong; Seung-Tak Ryu; Gyu-Hyeong Cho (ISSCC, 2012)

A sampling-based 128×128 direct photon-counting X-ray image sensor with 3 energy bins and spatial resolution of 60μm/pixel. - Hyunsik Kim; Sang-Wook Han; Junhyeok Yang; Sung-il Kim; Young Kim; Sangwook Kim; Dae-Kun Yoon; Jun Su Lee; Jae-Chul Park; Younghun Sung; Seong-Deok Lee; Seung-Tak Ryu; et al. (ISSCC, 2012)

A Single-Supply 84 dB DR Audio-Band ADC for Compact Digital Microphones. - Huy-Binh Le; Sang-Gug Lee 001; Seung-Tak Ryu (IEICE Trans. Electron., 2012)

A 180-µW, 120-MHz, Fourth Order Low-Pass Bessel Filter Based on FVF Biquad Structure. - Hundo Shin; Seung-Tak Ryu (IEICE Trans. Electron., 2012)

A 40 mV Transformer-Reuse Self-Startup Boost Converter With MPPT Control for Thermoelectric Energy Harvesting. - Jong-Pil Im; Se-Won Wang; Seung-Tak Ryu; Gyu-Hyeong Cho (IEEE J. Solid State Circuits, 2012)

A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm. - Sang-Hyun Cho; Chang-Kyo Lee; Sang-Gug Lee 001; Seung-Tak Ryu (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An 8.6 ENOB 900MS/s time-interleaved 2b/cycle SAR ADC with a 1b/cycle reconfiguration for resolution enhancement. - Hyeok-Ki Hong; Hyun-Wook Kang; Barosaim Sung; Choong-Hoon Lee; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2013)

A 5.6mV inter-channel DVO 10b column-driver IC with mismatch-free switched-capacitor interpolation for mobile active-matrix LCDs. - Hyunsik Kim; Junhyeok Yang; Sang-Hui Park; Seung-Tak Ryu; Gyu-Hyeong Cho (ISSCC, 2013)

A highly noise-immune touch controller using Filtered-Delta-Integration and a charge-interpolation technique for 10.1-inch capacitive touch-screen panels. - Junhyeok Yang; Sang-Hui Park; Jung-Min Choi; Hyunsik Kim; Changbyung Park; Seung-Tak Ryu; Gyu-Hyeong Cho (ISSCC, 2013)

An Asynchronous Sampling-Based 128x128 Direct Photon-Counting X-Ray Image Detector with Multi-Energy Discrimination and High Spatial Resolution. - Hyunsik Kim; Sang-Wook Han; Junhyeok Yang; Sung-il Kim; Young Kim; Sangwook Kim; Dae-Kun Yoon; Jun Su Lee; Jae-Chul Park; Younghun Sung; Seong-Deok Lee; Seung-Tak Ryu; et al. (IEEE J. Solid State Circuits, 2013)

A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. - Jong-In Kim; Ba-Ro-Saim Sung; Wan Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2013)

An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers. - Seung-Yeob Baek 002; Jae-Kyum Lee; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design. - Chang-Kyo Lee; Wan Kim; Hyun-Wook Kang; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A Noise-Immune High-Speed Readout Circuit for In-Cell Touch Screen Panels. - Junhyeok Yang; Seungchul Jung; Young-Suk Son; Seung-Tak Ryu; Gyu-Hyeong Cho (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. - Ji-Wook Kwon; Dong-Hwan Jin; Hyeon-June Kim; Sun-Il Hwang; Min-Chul Shin; Jong-Ho Kang; Seung-Tak Ryu (CICC, 2014)

23.5 An energy pile-up resonance circuit extracting maximum 422% energy from piezoelectric material in a dual-source energy-harvesting interface. - Young-Sub Yuk; Seungchul Jung; Hui-Dong Gwon; Sukhwan Choi; Si-Duk Sung; Tae-Hwang Kong; Sung-Wan Hong; Jun-Han Choi; Min-Yong Jeong; Jong-Pil Im; Seung-Tak Ryu; Gyu-Hyeong Cho (ISSCC, 2014)

A 10-Bit Column-Driver IC With Parasitic-Insensitive Iterative Charge-Sharing Based Capacitor-String Interpolation for Mobile Active-Matrix LCDs. - Hyunsik Kim; Junhyeok Yang; Sang-Hui Park; Seung-Tak Ryu; Gyu-Hyeong Cho (IEEE J. Solid State Circuits, 2014)

A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications. - Ghil-Geun Oh; Chang-Kyo Lee; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Delta readout scheme for image-dependent power savings in a CMOS image sensor with multi-column-parallel SAR ADCs. - Hyeon-June Kim; Sun-Il Hwang; Ji-Wook Kwon; Dong-Hwan Jin; Byoung Soo Choi; Sang-Gwon Lee; Jong-Ho Park; Jang-Kyoo Shin; Seung-Tak Ryu (A-SSCC, 2015)

A 6-bit 10-GS/s 63-mW 4x TI time-domain interpolating flash ADC in 65-nm CMOS. - Dong-Ryeol Oh; Jong-In Kim; Min-Jae Seo; Jin-Gwang Kim; Seung-Tak Ryu (ESSCIRC, 2015)

26.7 A 2.6b/cycle-architecture-based 10b 1 JGS/s 15.4mW 4×-time-interleaved SAR ADC with a multistep hardware-retirement technique. - Hyeok-Ki Hong; Hyun-Wook Kang; Dong-Shin Jo; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

Session 15 overview: Data-converter techniques: Data converters subcommittee. - Seung-Tak Ryu; Matt Straayer (ISSCC, 2015)

26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. - Ba-Ro-Saim Sung; Dong-Shin Jo; Il-Hoon Jang; Dong-Suk Lee; Yong-Sang You; Yong-Hee Lee; Ho-Jin Park; Seung-Tak Ryu (ISSCC, 2015)

Ternary-level thermometer C-DAC switching scheme for flash-assisted SAR ADCs. - Hyun-Wook Kang; Hyeok-Ki Hong; Sanghoon Park; Ki-Jin Kim; Kwang-Ho Ahn; Seung-Tak Ryu (IEICE Electron. Express, 2015)

A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC. - Hyeok-Ki Hong; Wan Kim; Hyun-Wook Kang; Sun-Jae Park; Michael Choi; Ho-Jin Park; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A 15 µm-Pitch, 8.7-ENOB, 13-Mcells/sec Logarithmic Readout Circuit for Multi-Level Cell Phase Change Memory. - Dong-Hwan Jin; Ji-Wook Kwon; Hyeon-June Kim; Sun-Il Hwang; Min-Chul Shin; Junho Cheon; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. - Jong-In Kim; Dong-Ryeol Oh; Dong-Shin Jo; Ba-Ro-Saim Sung; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2015)

A 54-μW fast-settling arterial pulse wave sensor for wrist watch type system. - Kwantae Kim; Minseo Kim; Hyunwoo Cho; Kwonjoon Lee; Seung-Tak Ryu; Hoi-Jun Yoo (ISCAS, 2016)

F2: Data-converter calibration and dynamic-matching techniques. - Kostas Doris; Alyosha C. Molnar; Xicheng Jiang; Seung-Tak Ryu (ISSCC, 2016)

A Delta-Readout Scheme for Low-Power CMOS Image Sensors With Multi-Column-Parallel SAR ADCs. - Hyeon-June Kim; Sun-Il Hwang; Ji-Wook Kwon; Dong-Hwan Jin; Byoung Soo Choi; Sang-Gwon Lee; Jong-Ho Park; Jang-Kyoo Shin; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2016)

A 0.6 V 12 b 10 MS/s Low-Noise Asynchronous SAR-Assisted Time-Interleaved SAR (SATI-SAR) ADC. - Wan Kim; Hyeok-Ki Hong; Yi-Ju Roh; Hyun-Wook Kang; Sun-Il Hwang; Dong-Shin Jo; Dong-Jin Chang; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2016)

A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs. - Hyun-Wook Kang; Hyeok-Ki Hong; Sanghoon Park; Ki-Jin Kim; Kwang-Ho Ahn; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2. - Si-Nai Kim; Mee-Ran Kim; Ba-Ro-Saim Sung; Hyun-Wook Kang; Min-Hyung Cho; Seung-Tak Ryu (IEEE Trans. Very Large Scale Integr. Syst., 2016)

F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TX. - Kostas Doris; David Robertson 002; Seung-Tak Ryu; Seng-Pan U (ISSCC, 2017)

An incremental zoom sturdy MASH ADC. - Ki-Hoon Seo; Il-Hoon Jang; Kyung-Jun Noh; Seung-Tak Ryu (MWSCAS, 2017)

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction. - Hyeon-June Kim; Sun-Il Hwang; Jae-Hyun Chung; Jong-Ho Park; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2017)

Introduction to the Special Issue on the 2017 IEEE International Solid-State Circuits Conference. - Tim Piessens; Seung-Tak Ryu; Chih-Ming Hung; Alyosha C. Molnar; Mounir Meghelli (IEEE J. Solid State Circuits, 2017)

Normalized-Full-Scale-Referencing Digital-Domain Linearity Calibration for SAR ADC. - Dong-Jin Chang; Wan Kim; Min-Jae Seo; Hyeok-Ki Hong; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Session 14 overview: High-resolution ADCs: Data converter subcommittee. - Matt Straayer; Seung-Tak Ryu; Un-Ku Moon (ISSCC, 2018)

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. - Il-Hoon Jang; Min-Jae Seo; Sang-Hyun Cho; Jae-Keun Lee; Seung-Yeob Baek 002; Sunwoo Kwon; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme. - Hyun-Wook Kang; Hyeok-Ki Hong; Wan Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

Introduction to the Special Section on the 2017 Asian Solid-State Circuits Conference (A-SSCC). - Tsung-Hsien Lin; Chia-Hsiang Yang; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration. - Dong-Jin Chang; Min-Jae Seo; Hyeok-Ki Hong; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 65-nm CMOS 6-Bit 20 GS/s Time-Interleaved DAC With Full-Binary Sub-DACs. - Si-Nai Kim; Woo-Cheol Kim; Min-Jae Seo; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-µm CMOS. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Sun-Il Hwang; Jong-Pal Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A Reusable Code-Based SAR ADC Design With CDAC Compiler and Synthesizable Analog Building Blocks. - Min-Jae Seo; Yi-Ju Roh; Dong-Jin Chang; Wan Kim; Ye-Dam Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Dong-Jin Chang; Won-Mook Lim; Jae-Hyun Chung; Chang-Un Park; Eun-Ji An; Seung-Tak Ryu (A-SSCC, 2019)

A 6b 28GS/s Four-channel Time-interleaved Current-Steering DAC with Background Clock Phase Calibration. - Woo-Cheol Kim; Dong-Shin Jo; Yi-Ju Roh; Ye-Dam Kim; Seung-Tak Ryu (VLSI Circuits, 2019)

A 40nm CMOS 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR ADC. - Min-Jae Seo; Ye-Dam Kim; Jae-Hyun Chung; Seung-Tak Ryu (VLSI Circuits, 2019)

Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC. - Chang-Kyo Lee; Seung-Tak Ryu (IET Circuits Devices Syst., 2019)

A Reference-Free Temperature-Dependency-Compensating Readout Scheme for Phase-Change Memory Using Flash-ADC-Configured Sense Amplifiers. - Dong-Hwan Jin; Ji-Wook Kwon; Min-Jae Seo; Mi-Young Kim; Min-Chul Shin; Seokjoon Kang; Junghyuk Yoon; Taek-Seung Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS. - Kyoung-Jun Moon; Dong-Shin Jo; Wan Kim; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8 $ times$ Time-Domain Interpolating Flash ADC With Sequential Slope-Matching Offset Calibration. - Dong-Ryeol Oh; Jong-In Kim; Dong-Shin Jo; Woo-Chul Kim; Dong-Jin Chang; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2019)

A 10 nV/rt Hz noise level 32-channel neural impedance sensing ASIC for local activation imaging on nerve section. - Jongpal Kim; Wonseok Lee; Junyeub Suh; Hyungwoo Lee; Kyu-Il Lee; Ho Young Ahn; Min-Jae Seo; Seung-Tak Ryu; Kirill Y. Aristovich; David S. Holder; Sang Joon Kim (EMBC, 2020)

An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers. - Dong-Ryeol Oh; Kyoung-Jun Moon; Won-Mook Lim; Ye-Dam Kim; Eun-Ji An; Seung-Tak Ryu (VLSI Circuits, 2020)

A Single-Supply CDAC-Based Buffer-Embedding SAR ADC With Skip-Reset Scheme Having Inherent Chopping Capability. - Min-Jae Seo; Dong-Hwan Jin; Ye-Dam Kim; Jong-Pal Kim; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2020)

Compact Mixed-Signal Convolutional Neural Network Using a Single Modular Neuron. - Dong-Jin Chang; Byeong-Gyu Nam; Seung-Tak Ryu (IEEE Trans. Circuits Syst., 2020)

A 28-nm CMOS 12-Bit 250-MS/s Voltage-Current-Time Domain 3-Stage Pipelined ADC. - Kyoung-Jun Moon; Dong-Ryeol Oh; Michael Choi; Seung-Tak Ryu (IEEE Trans. Circuits Syst., 2020)

A 40-nm CMOS 12b 120-MS/s Nonbinary SAR-Assisted SAR ADC With Double Clock-Rate Coarse Decision. - Yi-Ju Roh; Dong-Jin Chang; Seung-Tak Ryu (IEEE Trans. Circuits Syst., 2020)

A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. - Dong-Shin Jo; Ba-Ro-Saim Sung; Min-Jae Seo; Woo-Cheol Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 4th-order CT I-DSM with Digital Noise Coupling and Input Pre-conversion Method for Initialization. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Dong-Jin Chang; Seung-Tak Ryu (A-SSCC, 2021)

An Input-buffer Embedding Dual-residue Pipelined-SAR ADC with Nonbinary Capacitive Interpolation. - Seung-Yong Lim; Raymond Mabilangan; Dong-Jin Chang; Young-Jae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2021)

MixedNet: Network Design Strategies for Cost-Effective Quantized CNNs. - Dong-Jin Chang; Byeong-Gyu Nam; Seung-Tak Ryu (IEEE Access, 2021)

A 28-nm 10-b 2.2-GS/s 18.2-mW Relative-Prime Time-Interleaved Sub-Ranging SAR ADC With On-Chip Background Skew Calibration. - Dong-Jin Chang; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2021)

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS. - Dong-Ryeol Oh; Kyoung-Jun Moon; Won-Mook Lim; Ye-Dam Kim; Eun-Ji An; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2021)

A Relative-Prime Rotation Based Fully On-Chip Background Skew Calibration for Time-Interleaved ADCs. - Dong-Jin Chang; Seung-Tak Ryu (VLSI Technology and Circuits, 2022)

A 7-Bit Two-Step Flash ADC With Sample-and-Hold Sharing Technique. - Dong-Ryeol Oh; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2022)

A 4th-Order Continuous-Time Delta-Sigma Modulator With Hybrid Noise-Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Gyeom-Je Bae; Dong-Hun Lee; Ye-Dam Kim; Hankyu Lee; Seong Joong Kim; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 25kHz-BW 97.4dB-SNDR 100.2dB-DR 3rd-Order SAR-Assisted CT DSM with 1-0 MASH and DNC. - Kent Edrian Lozada; Dong-Hun Lee; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2023)

An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Min-Jae Seo; Seung-Tak Ryu (CICC, 2023)

A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration. - Chang-Un Park; Jae-Hyun Chung; Seung-Tak Ryu (CICC, 2023)

A 28nm CMOS 12-bit-600-MS/s 15.6mW Pipelined ADC with Two-Stage Gainboosting FIA-based RA. - Bo Gao; Lizhen Zhang; Raymond Mabilangan; Chang-Un Park; Kent Edrian Lozada; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (A-SSCC, 2024)

TID-Tolerant StrongARM Comparator and Sampling Network for Satellite Application High-Voltage ADCs. - Charlie Tahar; Changyeop Lee; Kun-Woo Park; Kent Edrian Lozada; Hyojun Kim; Ki-Ho Kwon; Seung-Tak Ryu (A-SSCC, 2024)

A 5× OSR 1MHz-BW 81dB-SNDR 5th-Order Noise-Shaping SAR ADC with Zero-Optimized 3rd-Order Integrator. - Lizhen Zhang; Bo Gao; Kun-Woo Park; Hyeongjin Kim; Kent Edrian Lozada; Ye-Dam Kim; Jianhui Wu 001; Seung-Tak Ryu (A-SSCC, 2024)

A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. - Ye-Dam Kim; Jae-Hyun Chung; Kent Edrian Lozada; Chang-Un Park; Kun-Woo Park; Kwan-Hoon Song; Young-Hun Moon; Min-Jae Seo; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (VLSI Technology and Circuits, 2024)

DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation. - Lizhen Zhang; Bo Gao; Kun-Woo Park; Kent Edrian Lozada; Raymond Mabilangan; Hyeongjin Kim; Jianhui Wu 001; Seung-Tak Ryu (IEEE Open J. Circuits Syst., 2024)

A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC. - Jae-Hyun Chung; Ye-Dam Kim; Chang-Un Park; Kun-Woo Park; Dong-Ryeol Oh; Min-Jae Seo; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

A 25-kHz-BW 97.4-dB-SNDR SAR-Assisted Continuous-Time 1-0 MASH Delta-Sigma Modulator With Digital Noise Coupling. - Dong-Hun Lee; Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2024)

An M-Metric Readout Circuit for MLC Phase-Change Memory With a Comparator-Based Push-Pull Bit-Line Driver. - Ji-Wook Kwon; Dong-Hwan Jin; Min-Jae Seo; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Continuous-Time Delta-Sigma Modulator with SAR-Assisted Digital Noise Coupling. - Kent Edrian Lozada; Il-Hoon Jang; Ye-Dam Kim; Seung-Tak Ryu (CICC, 2025)

A 0.38-mW 200-kHz-BW Digital-Intensive Single-Opamp Fourth-Order Continuous-Time Delta-Sigma Modulator With Third-Order Digital Noise Coupling in 28-nm CMOS. - Kent Edrian Lozada; Ye-Dam Kim; Ho-Jin Kim; Youngjae Cho; Michael Choi; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2025)