A 60 to 200MHz SSCG with approximate Hershey-Kiss modulation profile in 0.11µm CMOS. - Seung-Wook Oh; Hyung-Min Park; Joon-Hyup Seo; Jae-Young Jang; Gi-Yeol Bae; Jin-Ku Kang (ISOCC, 2012)

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. - Jin-Cheol Seo; Sang-Soon Im; Kwan-Hee Yoon; Seung-Wook Oh; Taek-Joon An; Gi-Yeol Bae; Jin-Ku Kang (SoCC, 2012)

Hierarchical organization of cortical and thalamic connectivity. - Julie A. Harris; Stefan Mihalas; Karla E. Hirokawa; Jennifer D. Whitesell; Hannah Choi; Amy Bernard; Phillip Bohn; Shiella Caldejon; Linzy Casal; Andrew Cho; Aaron Feiner; David Feng 001; et al. (Nat., 2019)