An 88-dB Max-SFDR 12-bit SAR ADC With Speed-Enhanced ADEC and Dual Registers. - Seung-Yeob Baek 002; Jae-Kyum Lee; Seung-Tak Ryu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 4.2-mW 10-MHz BW 74.4-dB SNDR Continuous-Time Delta-Sigma Modulator With SAR-Assisted Digital-Domain Noise Coupling. - Il-Hoon Jang; Min-Jae Seo; Sang-Hyun Cho; Jae-Keun Lee; Seung-Yeob Baek 002; Sunwoo Kwon; Michael Choi; Hyungjong Ko; Seung-Tak Ryu (IEEE J. Solid State Circuits, 2018)

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. - Byoung-Joo Yoo; Dong-Hyuk Lim; Hyonguk Pang; June-Hee Lee; Seung-Yeob Baek 002; Naxin Kim; Dong-Ho Choi; Young-Ho Choi; Hyeyeon Yang; Taehun Yoon; Sang-Hyeok Chu; Kangjik Kim; et al. (ISSCC, 2020)

A 12b 600MS/s Pipelined SAR and 2x-Interleaved Incremental Delta-Sigma ADC with Source-Follower-Based Residue-Transfer Scheme in 7nm FinFET. - Seung-Yeob Baek 002; Il-Hoon Jang; Michael Choi; Hyungdong Roh; Woongtaek Lim; Youngjae Cho; Jongshin Shin (ISSCC, 2021)