A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture. - Kibong Koo; Sunghwa Ok; Yonggu Kang; Seungbong Kim; Choungki Song; Hyeyoung Lee; Hyungsoo Kim; Yongmi Kim; Jeonghun Lee; Seunghan Oak; Yosep Lee; Jungyu Lee 002; et al. (ISSCC, 2012)

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Reduced Variation of Decision Threshold Voltage. - Jungmin Yoon; Hyungrok Do; Daehyun Koh; Seunghan Oak; Junphyo Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2020)