INTERPRET: Inter-Warp Register Reuse for GPU Tensor Core. - Jae Seok Kwak; Myung Kuk Yoon; Ipoom Jeong; Seunghyun Jin 002; Won Woo Ro (PACT, 2023)

SHREG: Mitigating register redundancy in GPUs. - Seunghyun Jin 002; Hyunwuk Lee; Jonghyun Lee; Junsung Kim 002; Won Woo Ro (J. Syst. Archit., 2024)