HK386: an x86-compatible 32-bit CISC microprocessor. - Chong-Min Kyung; In-Cheol Park; Se-Kyoung Hong; K. S. Seong; B. S. Kong; Seungjong Lee; Hoon Choi; S. R. Maeng; D. T. Kim; Jong-Sun Kim; S. H. Park; Y. J. Kang (ASP-DAC, 1997)

Verification methodology of compatible microprocessors. - Joon-Seo Yim; Chang-Jae Park; Woo-Seung Yang; Hun-Seung Oh; Hee-Choul Lee; Hoon Choi; Tae-Hoon Kim; Seungjong Lee; Nara Won; Yung-Hei Lee; In-Cheol Park; Chong-Min Kyung (ASP-DAC, 1997)

Virtual Chip: Making Functional Models Work on Real Target Systems. - Namseung Kim; Hoon Choi; Seungjong Lee; Seungwang Lee; In-Cheol Park; Chong-Min Kyung (DAC, 1998)

Verification of a Microprocessor Using Real World Applications. - You-Sung Chang; Seungjong Lee; In-Cheol Park; Chong-Min Kyung (DAC, 1999)

Interface synthesis between software chip model and target board. - Seungjong Lee; Ando Ki; In-Cheol Park; Chong-Min Kyung (J. Syst. Archit., 2002)

A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. - James Lin; Daehwa Paik; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (CICC, 2013)

A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (CICC, 2013)

Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. - Zule Xu; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. - James Lin; Daehwa Paik; Seungjong Lee; Masaya Miyahara; Akira Matsuzawa (IEEE J. Solid State Circuits, 2015)

An 8-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor with 60 Mel-Frequency Energy Features Enabling 95% Speech Recognition Accuracy. - Seungjong Lee; Taewook Kang; John Bell; Mohammad R. Haghighat; Alberto J. Martinez; Michael P. Flynn (VLSI Circuits, 2020)

A 50μW 4-channel 83dBA-SNDR Speech Recognition Front-End with Adaptive Beamforming and Feature Extraction. - Taewook Kang; Seungjong Lee; Mohammad Haghigat; Darren Abramson 002; Michael P. Flynn (CICC, 2021)

6GS/s 8-channel CIC SAR TI-ADC with Neural Network Calibration. - Evelyn Ware; Justin M. Correll; Seungjong Lee; Michael P. Flynn (ESSCIRC, 2022)

A Multimode 157μW 4-Channel 80dBA-SNDR Speech-Recognition Frontend With Self-DOA Correction Adaptive Beamformer. - Taewook Kang; Seungjong Lee; Seungheun Song; Mohammad R. Haghighat; Michael P. Flynn (ISSCC, 2022)

An 8-bit 20.7 TOPS/W Multi-Level Cell ReRAM-based Compute Engine. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (VLSI Technology and Circuits, 2022)

An 81.6dB SNDR 15.625MHz BW 3rd Order CT SDM with a True TI NS Quantizer. - Seungjong Lee; Taewook Kang; Seungheun Song; Kyumin Kwon; Michael P. Flynn (VLSI Technology and Circuits, 2022)

An Eight-Element Frequency-Selective Acoustic Beamformer and Bitstream Feature Extractor. - Seungjong Lee; Taewook Kang; John Bell; Mohammad R. Haghighat; Alberto J. Martinez; Michael P. Flynn (IEEE J. Solid State Circuits, 2022)

A 0.024mm² 84.2dB-SNDR 1MHz-BW 3rd-Order VCO-Based CTDSM with NS-SAR Quantizer (NSQ VCO CTDSM). - Hsiang-Wen Chen; Seungjong Lee; Michael P. Flynn (VLSI Technology and Circuits, 2023)

A 150-MS/s Fully Dynamic SAR-Assisted Pipeline ADC Using a Floating Ring Amplifier and Gain-Enhancing Miller Negative-C. - Seungheun Song; Taewook Kang; Seungjong Lee; Michael P. Flynn (VLSI Technology and Circuits, 2023)

An 81.6 dB SNDR 15.625 MHz BW Third-Order CT SDM With a True Time-Interleaving Noise-Shaping Quantizer. - Seungjong Lee; Taewook Kang; Seungheun Song; Kyumin Kwon; Michael P. Flynn (IEEE J. Solid State Circuits, 2023)

An Anti-Aliasing-Filter-Assisted 3rd-Order VCO-Based CTDSM With NS-SAR Quantizer. - Hsiang-Wen Chen; Seungjong Lee; Michael P. Flynn (IEEE J. Solid State Circuits, 2024)

A Multimode 157 μW 4-Channel 80 dBA-SNDR Speech Recognition Frontend With Direction-of-Arrival Correction Adaptive Beamformer. - Taewook Kang; Seungjong Lee; Seungheun Song; Mohammad Reza Haghighat; Michael P. Flynn (IEEE J. Solid State Circuits, 2024)

An 8-bit 20.7 TOPS/W Multilevel Cell ReRAM Macro With ADC-Assisted Bit-Serial Processing. - Justin M. Correll; Lu Jie 001; Seungheun Song; Seungjong Lee; Junkang Zhu; Wei Tang 010; Luke Wormald; Jack Erhardt; Nicolas Breil; Roger Quon; Deepak Kamalanathan; Siddarth A. Krishnan; et al. (IEEE J. Solid State Circuits, 2025)