Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation. - Jinseob Jeong; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2008)

Multiobjective optimization of sleep vector for zigzag power-gated circuits in standard cell elements. - Seungwhun Paik; Youngsoo Shin (DAC, 2008)

Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. - Hyein Lee 003; Seungwhun Paik; Youngsoo Shin (ICCAD, 2008)

Register allocation for high-level synthesis using dual supply voltages. - Insup Shin; Seungwhun Paik; Youngsoo Shin (DAC, 2009)

HLS-l: High-level synthesis of high performance latch-based circuits. - Seungwhun Paik; Insup Shin; Youngsoo Shin (DATE, 2009)

Retiming and time borrowing: Optimizing high-performance pulsed-latch-based circuits. - Seonggwan Lee; Seungwhun Paik; Youngsoo Shin (ICCAD, 2009)

Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. - Youngsoo Shin; Seungwhun Paik; Hyung-Ock Kim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Statistical time borrowing for pulsed-latch circuit designs. - Seungwhun Paik; Lee-eun Yu; Youngsoo Shin (ASP-DAC, 2010)

Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design. - Jun Seomun; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2010)

Wakeup synthesis and its buffered tree construction for power gating circuit designs. - Seungwhun Paik; Sangmin Kim; Youngsoo Shin (ISLPED, 2010)

Pulse Width Allocation and Clock Skew Scheduling: Optimizing Sequential Circuits Based on Pulsed Latches. - Hyein Lee 003; Seungwhun Paik; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. - Seungwhun Paik; Insup Shin; Taewhan Kim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. - Donkyu Baek; Insup Shin; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2011)

Pulser gating: A clock gating of pulsed-latch circuits. - Sangmin Kim; Inhak Han; Seungwhun Paik; Youngsoo Shin (ASP-DAC, 2011)

Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power. - Seungwhun Paik; Gi-Joon Nam; Youngsoo Shin (ICCAD, 2011)

Pulsed-Latch Circuits: A New Dimension in ASIC Design. - Youngsoo Shin; Seungwhun Paik (IEEE Des. Test Comput., 2011)

Sampling Correlation Sources for Timing Yield Analysis of Sequential Circuits with Clock Networks. - Lee-eun Yu; Changsik Shin; Seungwhun Paik; Jing-Jia Liou; Youngsoo Shin (J. Circuits Syst. Comput., 2011)

Retiming Pulsed-Latch Circuits With Regulating Pulse Width. - Seungwhun Paik; Seonggwan Lee; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Clock Gating Synthesis of Pulsed-Latch Circuits. - Seungwhun Paik; Inhak Han; Sangmin Kim; Youngsoo Shin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. - Insup Shin; Seungwhun Paik; Dongwan Shin; Youngsoo Shin (IEEE Trans. Very Large Scale Integr. Syst., 2012)

HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. - Youngsoo Shin; Insup Shin; Donkyu Baek; Duckhwan Kim 001; Seungwhun Paik (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Wakeup scheduling and its buffered tree synthesis for power gating circuits. - Sangmin Kim; Seungwhun Paik; Seokhyeong Kang; Youngsoo Shin (Integr., 2016)