M-folding method-based elliptic curve cryptosystem for industrial cyber-physical system. - Tae Hoon Do; Seungwoo Park; Jaehwan Lee 003; Sangoh Park (Int. J. Distributed Sens. Networks, 2019)

A 1.3-4-GHz Quadrature-Phase Digital DLL Using Sequential Delay Control and Reconfigurable Delay Line. - Hyunsu Park; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Gyutae Park; Jinil Chung; Kyeong-Min Kim; Hae-Kang Jung; Hyungsoo Kim; Junhyun Chun; et al. (IEEE J. Solid State Circuits, 2021)

Analysis of a Multiwire, Multilevel, and Symbol Correlation Combination Scheme. - Jonghyuck Choi; Yoonjae Choi; Hyunsu Park; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 15 Gb/s Non-Return-to-Zero Transmitter With 1-Tap Pre-Emphasis Feed-Forward Equalizer for Low-Power Ground Terminated Memory Interfaces. - Youngwook Kwon; Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Seungwoo Park; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 0.83pJ/b 52Gb/s PAM-4 Baud-Rate CDR with Pattern-Based Phase Detector for Short-Reach Applications. - Seungwoo Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Hyunsu Park; Youngwook Kwon; Chulwoo Kim (ISSCC, 2023)

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces. - Yoonjae Choi; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Chulwoo Kim (IEEE J. Solid State Circuits, 2023)

A 33-Gb/s/Pin 1.09-pJ/Bit Single-Ended PAM-3 Transceiver With Ground-Referenced Signaling and Time-Domain Decision Technique for Multi-Chip Module Memory Interfaces. - Youngwook Kwon; Hyunsu Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Seungwoo Park; Kyeong-Min Kim; Changkyu Choi; Hae-Kang Jung; Chulwoo Kim (IEEE J. Solid State Circuits, 2023)

A 16-Gb/s NRZ Receiver With 0.0019-pJ/bit/dB 1-Tap Charge-Redistribution DFE. - Jonghyuck Choi; Yoonjae Choi; Hyunsu Park; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector. - Yoonjae Choi; Hyunsu Park; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Changmin Sim; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications. - Hyunjin Kim; ChangHun Park; Inho Park; Taehyeong Park; Seungwoo Park; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces. - Jonghyuck Choi; Yoonjae Choi; Jincheol Sim; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances. - Jincheol Sim; Changmin Sim; Hyunsu Park; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Jong-Min Kim; Ju-Hyung Lee 001; Young-Chai Ko; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces. - Hyoshin Kang; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques. - Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Hwaseok Shin; Junseob So; Seonbeen Lee; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling. - Seungwoo Park; Yoonjae Choi; Jonghyuck Choi; Jincheol Sim; Youngwook Kwon; Changmin Sim; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces. - Seongcheol Kim; Jincheol Sim; Yoonjae Choi; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Changmin Sim; Junseob So; Taehyeong Park; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces. - Seongcheol Kim; Changmin Sim; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Junseob So; Hwaseok Shin; Seonbeen Lee; Chulwoo Kim (IEEE J. Solid State Circuits, 2024)

A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces. - Yoonjae Choi; Changmin Sim; Jonghyuck Choi; Jincheol Sim; Hyunsu Park; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

22.5 A 0.3pJ/b 32Gb/s/Pin Single-Ended PAM-4 Receiver with a Delay-Less Capacitive-Feedback Equalizer. - Junseob So; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Hwaseok Shin; Seonbeen Lee; Taehwan Kim; Chulwoo Kim (ISSCC, 2025)

A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM. - Taehwan Kim; Changmin Sim; Seungwoo Park; Jinwoo Park; Seongcheol Kim; Hwaseok Shin; Junseob So; Seonbeen Lee; Youngwook Kwon; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A 28-Gb/s Single-Ended PAM-4 Transceiver With Active-Inductor Equalizer and Amplitude- Detection LSB Decoder for Memory Interfaces. - Hwaseok Shin; Hyoshin Kang; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Youngwook Kwon; Seungwoo Park; Seongcheol Kim; Changmin Sim; Junseob So; Taehwan Kim; Chulwoo Kim (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 50 Gb/s PAM-4 Transceiver With High-Swing Driver, Dual-Loop Analog Equalizer, and Integrator-Based Baud-Rate Linear CDR for Short-Reach Links. - Jincheol Sim; Changmin Sim; Jonghyuck Choi; Seungwoo Park; Seongcheol Kim; Chulwoo Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A 52-Gb/s Low-Power PAM-4 Baud-Rate CDR Using Pattern-Based Phase Detector for Short-Reach Applications. - Seungwoo Park; Yoonjae Choi; Jincheol Sim; Jonghyuck Choi; Hyunsu Park; Youngwook Kwon; Changmin Sim; Seongcheol Kim; Chulwoo Kim (IEEE J. Solid State Circuits, 2025)