3D integration technology for set-top box application. - David Henry; Séverine Cheramy; Jean Charbonnier; Pascal Chausse; Muriel Neyret; Cathy Brunet-Manquat; Sophie Verrun; Nicolas Sillon; Laurent Bonnot; Xavier Gagnard; E. Saugier (3DIC, 2009)

3D integration demonstration of a wireless product with design partitioning. - G. Druais; Pascal Ancey; C. Aumont; V. Caubet; Laurent-Luc Chapelon; C. Chaton; Séverine Cheramy; S. Cordova; E. Cirot; Jean-Philippe Colonna; Perceval Coudrain; T. Divel; et al. (3DIC, 2011)

RF characterization of substrate coupling between TSV and MOS transistors in 3D integrated circuits. - Melanie Brocard; Cédric Bermond; Thierry Lacrevaz; Alexis Farcy; Patrick Le Maitre; P. Scheer; Patrick Leduc; Séverine Cheramy; Bernard Fléchet (3DIC, 2013)

Wafer level encapsulated materials evaluation for chip on wafer (CoW) approach in 2.5D Si interposer integration. - Sylvain Joblot; Alexis Farcy; Nicolas Hotellier; Amadine Jouve; François de Crecy; Arnaud Garnier; M. Argoud; C. Ferrandon; J.-P. Colonna; R. Franiatte; C. Laviron; Séverine Cheramy (3DIC, 2013)

Which interconnects for which 3D applications? Status and perspectives. - Yann Lamy; Jean-Philippe Colonna; G. Simon; Patrick Leduc; Séverine Cheramy; C. Laviron (3DIC, 2013)

Thermal correlation between measurements and FEM simulations in 3D ICs. - Papa Momar Souare; François de Crecy; Vincent Fiori; M. Haykel Ben Jamaa; Alexis Farcy; Sébastien Gallois-Garreignot; Andras Borbely; Jean-Philippe Colonna; Perceval Coudrain; B. Giraud; C. Laviron; Séverine Cheramy; et al. (3DIC, 2013)

Silicon based dry-films evaluation for 2.5D and 3D Wafer-Level system integration improvement. - Amadine Jouve; Y. Sinquin; Arnaud Garnier; M. Daval; Pascal Chausse; M. Argoud; N. Allouti; Laurence Baud; Jérôme Dechamp; R. Franiatte; Séverine Cheramy; H. Kato; et al. (3DIC, 2015)

3D advanced integration technology for heterogeneous systems. - Pascal Vivet; Christian Bernard; Fabien Clermidy; Denis Dutoit; Eric Guthmuller; Ivan Miro Panades; Gaël Pillonnet; Yvain Thonnart; Arnaud Garnier; Didier Lattard; Amandine Jouve; Franck Bana; et al. (3DIC, 2015)

Towards high density 3D interconnections. - Séverine Cheramy; Amadine Jouve; Lucile Arnaud; Claire Fenouillet-Béranger; Perrine Batude; Maud Vinet (3DIC, 2016)

ITAC: A complete 3D integration test platform. - Didier Lattard; Lucile Arnaud; Arnaud Garnier; Nicolas Bresson; Franck Bana; R. Segaud; Amadine Jouve; H. Jacquinot; Stéphane Moreau; Karim Azizi-Mourier; C. Chantre; Pascal Vivet; et al. (3DIC, 2016)

Heat spreading packaging solutions for hybrid bonded 3D-ICs. - Rafael Prieto; Perceval Coudrain; Jean-Philippe Colonna; Y. Hallez; Christian Chancel; Venceslass Rat; Sylvain Dumas; G. Romano; R. Franiatte; C. Brunet-Manquiat; Séverine Cheramy; Alexis Farcy (3DIC, 2016)

8.1 A 4×4×2 homogeneous scalable 3D network-on-chip circuit with 326MFlit/s 0.66pJ/b robust and fault-tolerant asynchronous 3D links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Cristiano Santos; Fabien Clermidy; Séverine Cheramy; Frédéric Pétrot; et al. (ISSCC, 2016)

Experimental Insights Into Thermal Dissipation in TSV-Based 3-D Integrated Circuits. - Perceval Coudrain; Papa Momar Souare; Rafael Prieto; Vincent Fiori; Alexis Farcy; Laurent Le Pailleur; Jean-Philippe Colonna; Cristiano Santos; Pascal Vivet; M. Haykel Ben Jamaa; Denis Dutoit; François de Crecy; et al. (IEEE Des. Test, 2016)

A 4 × 4 × 2 Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links. - Pascal Vivet; Yvain Thonnart; Romain Lemaire; Cristiano Santos; Edith Beigné; Christian Bernard; Florian Darve; Didier Lattard; Ivan Miro Panades; Denis Dutoit; Fabien Clermidy; Séverine Cheramy; et al. (IEEE J. Solid State Circuits, 2017)

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. - Eric Guthmuller; César Fuguet Tortolero; Pascal Vivet; Christian Bernard; Ivan Miro Panades; Jean Durupt; E. Beignc; Didier Lattard; Séverine Cheramy; Alain Greiner; Quentin L. Meunier; Pirouz Bazargan-Sabet (ESSCIRC, 2018)

Towards a Complete Direct Hybrid Bonding D2W Integration Flow: Known-Good-Dies and Die Planarization Modules Development. - Emilie Bourjot; Paul Stewart; Christophe Dubarry; E. Lagoutte; E. Rolland; Nicolas Bresson; G. Romano; D. Scevola; Viorel Balan; Jérôme Dechamp; Marc Zussy; Gaëlle Mauguen; et al. (3DIC, 2019)

Advanced 3D Technologies and Architectures for 3D Smart Image Sensors. - Pascal Vivet; Gilles Sicard; Laurent Millet; Stéphane Chevobbe; Karim Ben Chehida; Luis Angel Cubero; Monte Alegre; Maxence Bouvier; Alexandre Valentian; Maria Lepecq; Thomas Dombek; Olivier Bichler; et al. (DATE, 2019)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)