An area- and power-efficient FIFO with error-reduced data compression for image/video processing. - Seyed Mohammad Ali Zeinolabedin; Jun Zhou 017; Xin Liu 015; Tony T. Kim (ISCAS, 2014)

A 0.5V power and area efficient Laplacian Pyramid processing engine using FIFO with adaptive data compression. - Seyed Mohammad Ali Zeinolabedin; Jun Zhou 017; Xin Liu 015; Tony T. Kim (ESSCIRC, 2015)

Design of a hybrid neural spike detection algorithm for implantable integrated brain circuits. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Kiat Seng Yeo; Tony Tae-Hyoung Kim (ISCAS, 2015)

An Area- and Energy-Efficient FIFO Design Using Error-Reduced Data Compression and Near-Threshold Operation for Image/Video Applications. - Seyed Mohammad Ali Zeinolabedin; Jun Zhou 017; Xin Liu 015; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Live demonstration: A 128-channel spike sorting processor featuring 0.175 μW and 0.0033 mm2 per Channel in 65-nm CMOS. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (APCCAS, 2016)

A 0.3 pJ/access 8T data-aware SRAM utilizing column-based data encoding for ultra-low power applications. - Anh-Tuan Do; Seyed Mohammad Ali Zeinolabedin; Tony Tae-Hyoung Kim (A-SSCC, 2016)

A 128-channel spike sorting processor featuring 0.175 µW and 0.0033 mm2 per channel in 65-nm CMOS. - Seyed Mohammad Ali Zeinolabedin; Anh-Tuan Do; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (VLSI Circuits, 2016)

Structuring of Contourlet Transform for Pipeline-Based Implementation. - Seyed Mohammad Ali Zeinolabedin; Nader Karimi; Shadrokh Samavi; Tony Tae-Hyoung Kim (Circuits Syst. Signal Process., 2016)

A Power and Area Efficient Ultra-Low Voltage Laplacian Pyramid Processing Engine With Adaptive Data Compression. - Seyed Mohammad Ali Zeinolabedin; Jun Zhou 017; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2016)

An Area-Efficient 128-Channel Spike Sorting Processor for Real-Time Neural Recording With 0.175µW/Channel in 65-nm CMOS. - Anh-Tuan Do; Seyed Mohammad Ali Zeinolabedin; Dongsuk Jeon; Dennis Sylvester; Tony Tae-Hyoung Kim (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Energy-Efficient Data-Aware SRAM Design Utilizing Column-Based Data Encoding. - Anh-Tuan Do; Seyed Mohammad Ali Zeinolabedin; Tony Tae-Hyoung Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Ultra-low Power and Area-efficient Hardware Accelerator for Adaptive Neural Signal Compression. - Qier Ma; Liyuan Guo; Seyed Mohammad Ali Zeinolabedin; Christian Mayr 001 (BioCAS, 2021)

Analyzing ARM CoreSight ETMv4.x Data Trace Stream with a Real-time Hardware Accelerator. - Seyed Mohammad Ali Zeinolabedin; Johannes Partzsch; Christian Mayr 001 (DATE, 2021)

Real-time Hardware Implementation of ARM CoreSight Trace Decoder. - Seyed Mohammad Ali Zeinolabedin; Johannes Partzsch; Christian Mayr 001 (IEEE Des. Test, 2021)

Various Distance Metrics Evaluation on Neural Spike Classification. - Shengpeng Guo; Liyuan Guo; Seyed Mohammad Ali Zeinolabedin; Christian Mayr 001 (BioCAS, 2022)

A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm. - Franz Marcus Schüffny; Stefan Hänzsche; Marc Berthel; Seyed Mohammad Ali Zeinolabedin; Stefan Scholze; Sebastian Höppner; Richard Miru George; Christian Mayr 001 (NorCAS, 2022)

How to design an input stage for neural recording system in 22 nm FDSOI. - Franz Marcus Schüffny; Sebastian Höppner; Seyed Mohammad Ali Zeinolabedin; Richard Miru George; Christian Mayr 001 (PRIME, 2022)

A 16-Channel Fully Configurable Neural SoC With 1.52 $ mu$W/Ch Signal Acquisition, 2.79 $ mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI. - Seyed Mohammad Ali Zeinolabedin; Franz Marcus Schüffny; Richard George 001; Florian Kelber; Heiner Bauer; Stefan Scholze; Stefan Hänzsche; Marco Stolba; Andreas Dixius; Georg Ellguth; Dennis Walter; Sebastian Höppner; et al. (IEEE Trans. Biomed. Circuits Syst., 2022)

An Ultra-Low Area Digital-Assisted Neuro Recording System in 22nm FDSOI Technology. - Franz Marcus Schüffny; Sebastian Höppner; Stefan Hänzsche; Richard Miru George; Seyed Mohammad Ali Zeinolabedin; Christian Mayr 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Low-Power Hardware Accelerator of MFCC Extraction for Keyword Spotting in 22nm FDSOI. - Liyuan Guo; Matthias Jobst; Johannes Partzsch; Stefan Scholze; Andreas Dixius; Matthias Lohrmann; Seyed Mohammad Ali Zeinolabedin; Christian Mayr 001 (AICAS, 2023)

A 16-channel Real-time Adaptive Neural Signal Compression Engine in 22nm FDSOI. - Liyuan Guo; Seyed Mohammad Ali Zeinolabedin; Franz Marcus Schüffny; Annika Weiße; Stefan Scholze; Richard George 001; Johannes Partzsch; Christian Mayr 001 (NEWCAS, 2023)

A 3.3V Saturation-Aware Neurostimulator with Reset Functionality in 22 nm FDSOI. - Franz Marcus Schüffny; Stefan Hänzsche; Stephan Henker; Seyed Mohammad Ali Zeinolabedin; Stefan Scholze; Sebastian Höppner; Richard Miru George; Christian Mayr 001 (NEWCAS, 2023)

Selecting IRN for AFE to Achieve Power-Area-Noise Efficiency in Next-Generation Neural Implants. - Seyed Mohammad Ali Zeinolabedin; Matthieu Couriol; Pierre-Emmanuel Gaillardon (MWSCAS, 2024)

NLU: An Adaptive, Small-Footprint, Low-Power Neural Learning Unit for Edge and IoT Applications. - Amirhossein Rostami; Seyed Mohammad Ali Zeinolabedin; Liyuan Guo; Florian Kelber; Heiner Bauer; Andreas Dixius; Stefan Scholze; Marc Berthel; Dennis Walter; Johannes Uhlig; Bernhard Vogginger; Christian Mayr 001 (IEEE Open J. Circuits Syst., 2025)